High Efficiency CMOS Class E Power Amplifier Using 0.13 μm Technology-0
This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-μm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged i...
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| Main Authors: | , , , , , |
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| Format: | E-Article |
| Language: | English |
| Published: |
IEEE
2012
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/16593/1/High%20Efficiency%20CMOS%20Class%20E%20Power%20Amplifier%28abstract%29.pdf http://ir.unimas.my/id/eprint/16593/ http://ieeexplore.ieee.org/document/6373883/ |
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| Summary: | This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-μm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with on-chip input and output impedance matching. The simulation results indicate that the PA delivers 11.9 dBm output power and 53% power added efficiency (PAE) with 1.3-V power supply into a 50-Ω load. The chip layout is 0.27 mm2. |
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