Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits

• Main Authors: Mohamad Imran, Bandan, Pagliarini, Samuel Nascimento, Mathew, Jimson, Pradhan, Dhiraj K.
• Format: Article
• Language: English
• Published: IOP Publishing 2017
• Subjects: T Technology (General)
• Online Access: http://ir.unimas.my/id/eprint/15964/1/Improved%20Multiple%20.pdf; http://ir.unimas.my/id/eprint/15964/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-85010660800&doi=10.1109%2fTR.2016.2643010&partnerID=40&md5=0bbf48890c97211f1d629aa421c6e59e

State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be made for this type of approach, to improve not only the error rates but also the performance of the placer itself. Thus, this paper proposes several improvements toward an efficient multiple faults-aware placement strategy. First, an analytical method to profile pair of gates is proposed. Second, we add another level of optimization to reduce the amount of wirelength observed after the placement is completed without jeopardizing the main objective (reliability). Third, we propose a way to manipulate white spaces between gates smartly, to separate the gates that are profiled as the most likely to reduce the error rate when paired adjacently in the circuit. Results show that a wirelength reduction of up to 61% is achieved. Also, additional reduction of the error rate of up to 23% can be achieved with only an overhead on placement execution time.