High throughput evaluation of SHA-1 implementation using unfolding transformation
Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C...
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| Main Authors: | , |
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| Format: | E-Article |
| Published: |
Asian Research Publishing Network (ARPN)
2016
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/12162/ http://www.arpnjournals.org/jeas/research_papers/rp_2016/jeas_0316_3812.pdf |
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