Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance

• Main Authors: Asrani, Lit, Nazreen, Junaidi, Shamsiah, Suhaili, Shirley, Rufus, Nor Asrina, Ramlee, Fariza, Mahyan
• Format: Proceeding
• Language: English
• Published: IEEE 2024
• Subjects: Q Science (General); T Technology (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://ir.unimas.my/id/eprint/46766/1/Evaluating_NoC_and_WiNoC_Architectures_for_Multicore_Architecture_Performance.pdf; http://ir.unimas.my/id/eprint/46766/; https://ieeexplore.ieee.org/document/10474757

To mitigate potential scalability challenges in future many-core architectures’ on-chip communication systems, the wireless Network-on-Chip (WiNoC) design concept has arisen as a compelling choice. It offers a viable approach to address these issues effectively. This paper delves into an extensive analysis of the performance evaluation concerning Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core multicore system. The study encompasses a thorough evaluation across four synthetic traffic profiles, namely random, shuffle, butterfly, and transpose traffic distributions, offering a comprehensive understanding of their impact on system performance.This evaluation involved a thorough analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy con-sumed. In order to substantiate our conclusions, we conducted simulations encompassing the 64-core mesh-based NoC and WiNoC architectures. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycle-accurate simulations. Analyzing the simulation outcomes, it becomes evident that the 64-core WiNoC architecture performs better in terms of network performance. This is evident from its ability to handle heavier workloads and achieve lower delays in all traffic situations, when compared to the 64-core NoC architecture.