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Junctionless transistors: parametric study with conventional doping in MOSFETS

Master of Science in Nanoelectronic Engineering

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Bibliographic Details
Main Author: Nurul Huda, Abdul Rahman
Other Authors: Mohd Khairuddin, Md. Arshad, Ir. Dr.
Format: Thesis
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2016
Subjects:
Metal oxide semiconductor field-effect transistors
Ultra-shallow junction
Junctionless
Transistor
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/77894
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spelling my.unimap-778942023-02-21T04:48:37Z Junctionless transistors: parametric study with conventional doping in MOSFETS Nurul Huda, Abdul Rahman Mohd Khairuddin, Md. Arshad, Ir. Dr. Metal oxide semiconductor field-effect transistors Ultra-shallow junction Junctionless Transistor Master of Science in Nanoelectronic Engineering The advancement of today technologies has been aggressively developed as the needs of current technology that becoming competitive and demanding to accommodate human lifestyle. The electronic gadgets drive the market with the requirements to provide efficient chip functionality at higher speed and extra functionality. This has become more challenging as the transistor density and performance are aggressively increasing. Thus, continuous downscaling of the conventional transistor will lead to severe short-channel effect (SCE), and one of the solutions is a ultra-shallow junction. Ultra-shallow junction is very challenging as it increases in fabrication cost and difficulty in the fabrication process. In this study, the channel, drain, and source have the same type of doping where the ultra-shallow junction has been eliminated. Hence, it is called junctionless. There will be no diffusion will take place where it will remove the high cost for ultrafast annealing techniques. Besides that, it allows the transistor to be fabricated with a shorter channel if the gradient of the doping concentration is zero between drain and channel or source and channel. This operation principle of the junctionless transistor is investigated through numerical simulations using technology computer aided design (TCAD) simulation tools. Firstly, the device performance of 3-Dimensional (3D) silicon-on-insulator (SOI) junctionless transistor (JLT) with 100 and 10 nm gate lengths, have been compared to the 3D SOI junction transistor (JT) with the same gate length. In order to achieve full depletion, the parameters such as metal gate workfunction, doping concentration, drain bias, and dimension are considered in the simulation process. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold slope, and draininduced- barrier-lowering are the main parameters that have been investigated. Following next is the characterization on the analog and radio frequency (RF) figures-of-merit. Based on the simulations, 1) the designated JLT device is more suitable to the higher gate workfunction of more than 5.0 eV whereas the designated JT device is more suitable with mid-gap values of gate workfunction of 4.6 eV. 2) the JLT transistor requires high gate work-function to have control over the channel. 3) the JT device is less sensitive to the variation of silicon body thickness (TSi) and width (WSi) compared to JLT. Lastly, the device performance on analog and RF figures of merit shows that no significant different between JLT and JT with the latter case shows slightly better performance, related to lower gate-to-gate capacitance (Cgg). 2016 2023-02-21T04:37:10Z 2023-02-21T04:37:10Z Thesis http://dspace.unimap.edu.my:80/xmlui/handle/123456789/77894 en Universiti Malaysia Perlis (UniMAP) Universiti Malaysia Perlis (UniMAP) Institute of Nano Electronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Metal oxide semiconductor field-effect transistors
Ultra-shallow junction
Junctionless
Transistor
spellingShingle Metal oxide semiconductor field-effect transistors
Ultra-shallow junction
Junctionless
Transistor
Nurul Huda, Abdul Rahman
Junctionless transistors: parametric study with conventional doping in MOSFETS
description Master of Science in Nanoelectronic Engineering
author2 Mohd Khairuddin, Md. Arshad, Ir. Dr.
author_facet Mohd Khairuddin, Md. Arshad, Ir. Dr.
Nurul Huda, Abdul Rahman
format Thesis
author Nurul Huda, Abdul Rahman
author_sort Nurul Huda, Abdul Rahman
title Junctionless transistors: parametric study with conventional doping in MOSFETS
title_short Junctionless transistors: parametric study with conventional doping in MOSFETS
title_full Junctionless transistors: parametric study with conventional doping in MOSFETS
title_fullStr Junctionless transistors: parametric study with conventional doping in MOSFETS
title_full_unstemmed Junctionless transistors: parametric study with conventional doping in MOSFETS
title_sort junctionless transistors: parametric study with conventional doping in mosfets
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2016
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/77894
_version_ 1772813065080799232
score 13.159267

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