Design of 100nm single-electron transistor (SET) by 2D TCAD simulation
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2009
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my.unimap-68882010-11-23T05:59:41Z Design of 100nm single-electron transistor (SET) by 2D TCAD simulation Amiza, Rasmi Uda, Hashim Awang Mat, Abd F Circuit simulation Integrated circuits -- Design and construction Single electron transistors Transistors Integrated circuit design Synopsys TCAD Link to publisher's homepage at http://ieeexplore.ieee.org One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with lOOnm gate length and 10nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 x 10-9 Watt for fixed current and 3.3565 x 10-9 Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation. 2009-08-13T08:36:18Z 2009-08-13T08:36:18Z 2006 Article p.367-372 0-7803-9730-4 http://ieeexplore.ieee.org/xpls/abs_all.jsp?=&arnumber=4266633 http://hdl.handle.net/123456789/6888 en Proceedings of the IEEE International Conference on Semiconductor Electronics (ICSE 06) Institute of Electrical and Electronics Engineering (IEEE) |
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Circuit simulation Integrated circuits -- Design and construction Single electron transistors Transistors Integrated circuit design Synopsys TCAD |
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Circuit simulation Integrated circuits -- Design and construction Single electron transistors Transistors Integrated circuit design Synopsys TCAD Amiza, Rasmi Uda, Hashim Awang Mat, Abd F Design of 100nm single-electron transistor (SET) by 2D TCAD simulation |
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Link to publisher's homepage at http://ieeexplore.ieee.org |
format |
Article |
author |
Amiza, Rasmi Uda, Hashim Awang Mat, Abd F |
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Amiza, Rasmi Uda, Hashim Awang Mat, Abd F |
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Amiza, Rasmi |
title |
Design of 100nm single-electron transistor (SET) by 2D TCAD simulation |
title_short |
Design of 100nm single-electron transistor (SET) by 2D TCAD simulation |
title_full |
Design of 100nm single-electron transistor (SET) by 2D TCAD simulation |
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Design of 100nm single-electron transistor (SET) by 2D TCAD simulation |
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Design of 100nm single-electron transistor (SET) by 2D TCAD simulation |
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design of 100nm single-electron transistor (set) by 2d tcad simulation |
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Institute of Electrical and Electronics Engineering (IEEE) |
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2009 |
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http://dspace.unimap.edu.my/xmlui/handle/123456789/6888 |
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1643788616667758592 |
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13.214268 |