Cover Image

Square & cube computation using Vedic Algorithms in FPGA

Link to publisher's homepage at http://ijneam.unimap.edu.my

Saved in:
Bibliographic Details
Main Authors: Kamaraj, A., Vidya, B., Sugapriya, M., Marichamy, P.
Other Authors: kamarajvlsi@gmail.com
Format: Article
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2020
Subjects:
Vedic Mathematics
Yavadunam sutra
Anurupyena sutra
Urdhva Tiryagbhyamsutra
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/65223
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.unimap-65223
record_format dspace
spelling my.unimap-652232020-06-24T04:10:07Z Square & cube computation using Vedic Algorithms in FPGA Kamaraj, A. Vidya, B. Sugapriya, M. Marichamy, P. kamarajvlsi@gmail.com Vedic Mathematics Yavadunam sutra Anurupyena sutra Urdhva Tiryagbhyamsutra Link to publisher's homepage at http://ijneam.unimap.edu.my Modern computational devices are in the thirst for speedy computation. Adders and multipliers are the major computational units. Various types of multiplier architectures are suggested so far towards faster computation of the product. The speed of the multipliers could be improved by reducing the number of steps required for obtaining the product. One of the methods to reduce the number of steps is Vedic mathematics. There are 16 sutras in ancient Vedic mathematics. This research aims to design a square and cube computation using the Vedic algorithms. Yavadunam sutra (whatever the extent of its deficiency) is used for squaring and Anurupyena sutra (proportionately) is used to compute the cube of the binary number. In the Yavadunam sutra, bit reduction technique is employed to obtain deficiency, thereby, reducing the bit size to N-1 bits. Thus, reduces the delay. Urdhva Tiryagbhyam sutra (vertical and crosswise) is an efficient algorithm used for the multiplication operation. The design was implemented on a Xilinx-Spartan6 (XC6SLX16) FPGA. 2020-06-24T04:10:07Z 2020-06-24T04:10:07Z 2020-04 Article International Journal of Nanoelectronics and Materials, vol.13(2), 2020, pages 315-322 1985-5761 (Printed) 1997-4434 (Online) http://dspace.unimap.edu.my:80/xmlui/handle/123456789/65223 http://ijneam.unimap.edu.my en Universiti Malaysia Perlis (UniMAP)
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Vedic Mathematics
Yavadunam sutra
Anurupyena sutra
Urdhva Tiryagbhyamsutra
spellingShingle Vedic Mathematics
Yavadunam sutra
Anurupyena sutra
Urdhva Tiryagbhyamsutra
Kamaraj, A.
Vidya, B.
Sugapriya, M.
Marichamy, P.
Square & cube computation using Vedic Algorithms in FPGA
description Link to publisher's homepage at http://ijneam.unimap.edu.my
author2 kamarajvlsi@gmail.com
author_facet kamarajvlsi@gmail.com
Kamaraj, A.
Vidya, B.
Sugapriya, M.
Marichamy, P.
format Article
author Kamaraj, A.
Vidya, B.
Sugapriya, M.
Marichamy, P.
author_sort Kamaraj, A.
title Square & cube computation using Vedic Algorithms in FPGA
title_short Square & cube computation using Vedic Algorithms in FPGA
title_full Square & cube computation using Vedic Algorithms in FPGA
title_fullStr Square & cube computation using Vedic Algorithms in FPGA
title_full_unstemmed Square & cube computation using Vedic Algorithms in FPGA
title_sort square & cube computation using vedic algorithms in fpga
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2020
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/65223
_version_ 1674067690386358272
score 13.160551

Similar Items