Implementing a large data bus VLIW microprocessor

Microprocessors have grown tremendously in its computing and data crunching capability since the early days of the invention of a microprocessor. Today, most microprocessors in the market are at 32 bits, while the latest microprocessors from IBM, Intel and AMD are at 64 bits. To further grow the com...

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Main Authors: Lee, Weng Fook, Ali Yeon, Md Shakaff
Format: Article
Language:English
Published: Science Publications. 2009
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Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/6437
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spelling my.unimap-64372009-07-14T04:12:50Z Implementing a large data bus VLIW microprocessor Lee, Weng Fook Ali Yeon, Md Shakaff Large data bus size microprocessor Multicore Microprocessors have grown tremendously in its computing and data crunching capability since the early days of the invention of a microprocessor. Today, most microprocessors in the market are at 32 bits, while the latest microprocessors from IBM, Intel and AMD are at 64 bits. To further grow the computational capability of a microprocessor, there are two possible paths. One method is to increase the data bus size of the microprocessor to 128/256/512 bits. The larger the data bus size, the more data can be crunched at any one time. The second method is to implement multiple microprocessor core in a single microprocessor unit. For example, Intel's Pentium 4 Dual Core and AMD's Athlon Dual Core both have two microprocessor core within a single microprocessor unit. Latest from Intel and AMD are quad core microprocessors with four microprocessor core within a single microprocessor unit. Both methods have its advantages and disadvantages. Both methods yields different design issues and have different engineering limitations. This research looks into the possibility of implementing a large data bus size VLIW microprocessor core of 256 bits on the data bus. VLIW is chosen as opposed to CISC and RISC due to its ease of scalability. 2009-07-14T04:12:49Z 2009-07-14T04:12:49Z 2008 Article American Journal of Applied Sciences , Volume 5, Issue 11, 2008, Pages 1528-1534 1546-9239 http://hdl.handle.net/123456789/6437 en Science Publications.
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Large data bus size microprocessor
Multicore
spellingShingle Large data bus size microprocessor
Multicore
Lee, Weng Fook
Ali Yeon, Md Shakaff
Implementing a large data bus VLIW microprocessor
description Microprocessors have grown tremendously in its computing and data crunching capability since the early days of the invention of a microprocessor. Today, most microprocessors in the market are at 32 bits, while the latest microprocessors from IBM, Intel and AMD are at 64 bits. To further grow the computational capability of a microprocessor, there are two possible paths. One method is to increase the data bus size of the microprocessor to 128/256/512 bits. The larger the data bus size, the more data can be crunched at any one time. The second method is to implement multiple microprocessor core in a single microprocessor unit. For example, Intel's Pentium 4 Dual Core and AMD's Athlon Dual Core both have two microprocessor core within a single microprocessor unit. Latest from Intel and AMD are quad core microprocessors with four microprocessor core within a single microprocessor unit. Both methods have its advantages and disadvantages. Both methods yields different design issues and have different engineering limitations. This research looks into the possibility of implementing a large data bus size VLIW microprocessor core of 256 bits on the data bus. VLIW is chosen as opposed to CISC and RISC due to its ease of scalability.
format Article
author Lee, Weng Fook
Ali Yeon, Md Shakaff
author_facet Lee, Weng Fook
Ali Yeon, Md Shakaff
author_sort Lee, Weng Fook
title Implementing a large data bus VLIW microprocessor
title_short Implementing a large data bus VLIW microprocessor
title_full Implementing a large data bus VLIW microprocessor
title_fullStr Implementing a large data bus VLIW microprocessor
title_full_unstemmed Implementing a large data bus VLIW microprocessor
title_sort implementing a large data bus vliw microprocessor
publisher Science Publications.
publishDate 2009
url http://dspace.unimap.edu.my/xmlui/handle/123456789/6437
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score 13.209306