Prototype of 16 BIT CPU on FPGA
Access is limited to UniMAP community.
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Learning Object |
| Language: | English |
| Published: |
Universiti Malaysia Perlis (UniMAP)
2016
|
| Subjects: | |
| Online Access: | http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42079 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| id |
my.unimap-42079 |
|---|---|
| record_format |
dspace |
| spelling |
my.unimap-420792016-06-16T06:59:45Z Prototype of 16 BIT CPU on FPGA Tamayanti, Ramasandram Dr Phak LenEh Kan 16 bit CPU Central Processing Unit (CPU) Central Processing Unit (CPU) -- Design and construction VHDL (Computer hardware description language) Access is limited to UniMAP community. This project is about Prototype of 16 bit CPU on FPGA. This prototyping of CPU uses the Very High Speed Integrated Circuit Hardware Description Language (VHDL) and the output will be displayed on the FPGA board. Few steps are implemented in this project which is the fetch, decode, execute and store. Besides that there are few components required to develop the CPU which are the Control Unit, ALU, Storage unit, datapath and also registers. The Datapath unit and Control unit plays the main role in this project. The input will send the data and instruction in 16 bit to the registers. The VHDL code will be written into the Quartus software and then executed. The result was displayed on the FPGA board. Finally this project has successfully develop prototyping 16-bit CPU on FPGA with hardware working as per the simulation. 2016-06-16T06:59:45Z 2016-06-16T06:59:45Z 2015-06 Learning Object http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42079 en Universiti Malaysia Perlis (UniMAP) School of Computer and Communication Engineering |
| institution |
Universiti Malaysia Perlis |
| building |
UniMAP Library |
| collection |
Institutional Repository |
| continent |
Asia |
| country |
Malaysia |
| content_provider |
Universiti Malaysia Perlis |
| content_source |
UniMAP Library Digital Repository |
| url_provider |
http://dspace.unimap.edu.my/ |
| language |
English |
| topic |
16 bit CPU Central Processing Unit (CPU) Central Processing Unit (CPU) -- Design and construction VHDL (Computer hardware description language) |
| spellingShingle |
16 bit CPU Central Processing Unit (CPU) Central Processing Unit (CPU) -- Design and construction VHDL (Computer hardware description language) Tamayanti, Ramasandram Prototype of 16 BIT CPU on FPGA |
| description |
Access is limited to UniMAP community. |
| author2 |
Dr Phak LenEh Kan |
| author_facet |
Dr Phak LenEh Kan Tamayanti, Ramasandram |
| format |
Learning Object |
| author |
Tamayanti, Ramasandram |
| author_sort |
Tamayanti, Ramasandram |
| title |
Prototype of 16 BIT CPU on FPGA |
| title_short |
Prototype of 16 BIT CPU on FPGA |
| title_full |
Prototype of 16 BIT CPU on FPGA |
| title_fullStr |
Prototype of 16 BIT CPU on FPGA |
| title_full_unstemmed |
Prototype of 16 BIT CPU on FPGA |
| title_sort |
prototype of 16 bit cpu on fpga |
| publisher |
Universiti Malaysia Perlis (UniMAP) |
| publishDate |
2016 |
| url |
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42079 |
| _version_ |
1643799904074596352 |
| score |
13.214268 |