Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput
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Universiti Malaysia Perlis (UniMAP)
2016
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| Online Access: | http://dspace.unimap.edu.my:80/xmlui/handle/123456789/41802 |
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my.unimap-418022016-06-01T03:42:34Z Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput Muhammad Fathi, Mohamad shakri Dr. Muataz Hameed Salih Al-Doori IIR filter Systolic approach Latency Nios II embedded evaluation kit (NEEK) Access is limited to UniMAP community. IIR implementation using systolic approach is for executing thickly pipelined bit parallel IIR filter are exhibited. The crucial issue of this project is system latency in sequential execution. Latency means delay between order and start to execute in sequential execution. This project is design to reduce and remove the latency during execution. Furthermore, the top level design as a block diagram to implement simple image processing system on Nios II Embedded Evaluation Kit (NEEK) board. This simple image processing system is implement with combination signal image processing module and systolic IIR filter. In addition, signal image processing module is important to combine with IIR filter to function well in a way of systolic approach. Systolic operation need to reuse input data many time to get accurate value before it is push to get perfect output. Therefore, this project achieve to enhance IIR implementation with systolic approach to get fast processing and better throughput. In conclusion, IIR get earlier stability after two round tested with simple image processing system. 2016-06-01T03:42:34Z 2016-06-01T03:42:34Z 2015-06 Learning Object http://dspace.unimap.edu.my:80/xmlui/handle/123456789/41802 en Universiti Malaysia Perlis (UniMAP) School of Computer and Communication Engineering |
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Universiti Malaysia Perlis |
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Asia |
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Malaysia |
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Universiti Malaysia Perlis |
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http://dspace.unimap.edu.my/ |
| language |
English |
| topic |
IIR filter Systolic approach Latency Nios II embedded evaluation kit (NEEK) |
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IIR filter Systolic approach Latency Nios II embedded evaluation kit (NEEK) Muhammad Fathi, Mohamad shakri Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput |
| description |
Access is limited to UniMAP community. |
| author2 |
Dr. Muataz Hameed Salih Al-Doori |
| author_facet |
Dr. Muataz Hameed Salih Al-Doori Muhammad Fathi, Mohamad shakri |
| format |
Learning Object |
| author |
Muhammad Fathi, Mohamad shakri |
| author_sort |
Muhammad Fathi, Mohamad shakri |
| title |
Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput |
| title_short |
Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput |
| title_full |
Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput |
| title_fullStr |
Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput |
| title_full_unstemmed |
Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput |
| title_sort |
enhance iir implementation on fpga using systolic approach for fast processing and better throughput |
| publisher |
Universiti Malaysia Perlis (UniMAP) |
| publishDate |
2016 |
| url |
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/41802 |
| _version_ |
1643799811653107712 |
| score |
13.214268 |