A particle swarm optimization approach for routing in VLSI

Proceeding of The 2nd International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN 2010) at Liverpool, United Kingdom on 28 July 2010 through 30 July 2010. Link to publisher's homepage at http://ezproxy.unimap.edu.my:2080/Xplore/dynhome.jsp

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Main Authors: Mohd Nasir, Ayob, Zulkifli, Md Yusof, Asrul, Adam, Amar Faiz, Zainal Abidin, Ismail, Ibrahim, Zuwairie, Ibrahim, Prof. madya, Shahdan, Sudin, Dr., Nasir, Shaikh Husin, Mohamed Khalil, Mohd Hani
Other Authors: khalil@fke.utm.my
Format: Working Paper
Language:English
Published: IEEE Conference Publications 2014
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Online Access:http://dspace.unimap.edu.my:80/dspace/handle/123456789/35339
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spelling my.unimap-353392014-06-11T02:05:17Z A particle swarm optimization approach for routing in VLSI Mohd Nasir, Ayob Zulkifli, Md Yusof Asrul, Adam Amar Faiz, Zainal Abidin Ismail, Ibrahim Zuwairie, Ibrahim, Prof. madya Shahdan, Sudin, Dr. Nasir, Shaikh Husin Mohamed Khalil, Mohd Hani khalil@fke.utm.my nasirsh@utm.my shahdan@fke.utm.my zuwairiee@fke.utm.my amarfaiz@fke.utm.my asruldm@gmail.com zmdyusof@fke.utm.my nasirayob@unimap.edu.my zuwairie@ump.edu.my Buffer insertion Interconnect Particle swarm optimization Routing Proceeding of The 2nd International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN 2010) at Liverpool, United Kingdom on 28 July 2010 through 30 July 2010. Link to publisher's homepage at http://ezproxy.unimap.edu.my:2080/Xplore/dynhome.jsp The performance of very large scale integration (VLSI) circuits is depends on the interconnected routing in the circuits. In VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path in routing is assumed having the minimum delay and better performance. However, the interconnect delay can be further improved if buffers are inserted at proper locations along the routing path. Hence, this paper proposes a heuristic technique to simultaneously find the optimal routing path and buffer location for minimal interconnect delay in VLSI based on particle swarm optimization (PSO). PSO is a robust stochastic optimization technique based on the movement and information sharing of swarms. In this study, location of doglegs is employed to model the particles that represent the routing solutions in VLSI. The proposed approach has a good potential in VLSI routing and can be further extended in future. 2014-06-11T02:05:17Z 2014-06-11T02:05:17Z 2010 Working Paper p. 49-53 978-076954158-7 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5614755&tag=1 http://dspace.unimap.edu.my:80/dspace/handle/123456789/35339 10.1109/CICSyN.2010.42 en Proceeding of The 2nd International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN 2010); IEEE Conference Publications
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Buffer insertion
Interconnect
Particle swarm optimization
Routing
spellingShingle Buffer insertion
Interconnect
Particle swarm optimization
Routing
Mohd Nasir, Ayob
Zulkifli, Md Yusof
Asrul, Adam
Amar Faiz, Zainal Abidin
Ismail, Ibrahim
Zuwairie, Ibrahim, Prof. madya
Shahdan, Sudin, Dr.
Nasir, Shaikh Husin
Mohamed Khalil, Mohd Hani
A particle swarm optimization approach for routing in VLSI
description Proceeding of The 2nd International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN 2010) at Liverpool, United Kingdom on 28 July 2010 through 30 July 2010. Link to publisher's homepage at http://ezproxy.unimap.edu.my:2080/Xplore/dynhome.jsp
author2 khalil@fke.utm.my
author_facet khalil@fke.utm.my
Mohd Nasir, Ayob
Zulkifli, Md Yusof
Asrul, Adam
Amar Faiz, Zainal Abidin
Ismail, Ibrahim
Zuwairie, Ibrahim, Prof. madya
Shahdan, Sudin, Dr.
Nasir, Shaikh Husin
Mohamed Khalil, Mohd Hani
format Working Paper
author Mohd Nasir, Ayob
Zulkifli, Md Yusof
Asrul, Adam
Amar Faiz, Zainal Abidin
Ismail, Ibrahim
Zuwairie, Ibrahim, Prof. madya
Shahdan, Sudin, Dr.
Nasir, Shaikh Husin
Mohamed Khalil, Mohd Hani
author_sort Mohd Nasir, Ayob
title A particle swarm optimization approach for routing in VLSI
title_short A particle swarm optimization approach for routing in VLSI
title_full A particle swarm optimization approach for routing in VLSI
title_fullStr A particle swarm optimization approach for routing in VLSI
title_full_unstemmed A particle swarm optimization approach for routing in VLSI
title_sort particle swarm optimization approach for routing in vlsi
publisher IEEE Conference Publications
publishDate 2014
url http://dspace.unimap.edu.my:80/dspace/handle/123456789/35339
_version_ 1643797771734482944
score 13.214268