Fabrication and characterization of engineered tunnel barrier for nonvolatile memory application

• Main Author: Zarimawaty, Zailan
• Format: Thesis
• Language: English
• Published: Universiti Malaysia Perlis (UniMAP) 2014
• Subjects: Non-volatile memory; Memory technology; Nonvolatile memory; Tunnel barrier; Memory device; Falsh memory device
• Online Access: http://dspace.unimap.edu.my:80/dspace/handle/123456789/31918

Non-volatile memory is a solid state memory device that can retain the stored information even when the power is turned-off; examples of a variety of ROMs and Flash Memory. Based on the charge storing mechanism, it can be divided into two main classes; floating gate and charge trapping devices. The most widely used device structure in contemporary memory technology is of a floating gate type. In this type of memory, electrons were transferred from the substrate to the floating gate, and vice versa in memory operations known as write and erase. For NAND Flash Memory architecture, these electrons transfer were carried out using tunneling mechanism known as Fowler-Nordheim tunneling, and its efficiency would determine the performance of a memory device. This mechanism takes place via ultra-thin dielectric layer, known as tunnel dielectric, which physically and electrically separates the floating gate from the substrate. Traditionally, thermally grown SiO2 thickness ranging from 5 nm to 10 nm is used as the tunnel dielectric. The 5 nm thicknesses is considered the intrinsic tunnel oxide limit, below which various leakages such as stress induced leakage current (SILC) and direct tunneling start to became a prominent limiting factors. Several efforts have been made to improve the flash memory cell performance by replacing the traditional SiO2 with various dielectric such as Oxynitride, and combinations of High-k materials. This study focuses on the Variable Oxide Thickness (VARIOT) approach of engineered tunnel barrier where the asymmetrical VARIOT structure with the effective oxide thickness (EOT) ranging from 6 nm to 14 nm were studied in the form of MOS capacitor structure. The tunneling current density in the VARIOT structure yield 108 A/cm2 at 15V programming voltage, compared to 105 A/cm2 for the conventional tunnel barrier with the same programming voltage. The results show that asymmetrical VARIOT tunnel barrier would significantly improves the floating gate memory-cell performance.