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Analysis of optimum dispatching policies for semiconductor fabrication

International Postgraduate Conference On Engineering (IPCE 2010), 16th - 17th October 2010 organized by Centre for Graduate Studies, Universiti Malaysia Perlis (UniMAP) at School of Mechatronic Engineering, Pauh Putra Campus, Perlis, Malaysia.

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Bibliographic Details
Main Authors: Mohd Azizi, Chik, Uda, Hashim, Prof. Dr.
Other Authors: Mohd_azizi@silterra.com
Format: Working Paper
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2012
Subjects:
First In First Out (FIFO)
Shortest Processing Cycle Time (SPT)
Critical Ratio (CR)
Earliest Due Date (EDD)
Shortest Remaining Processing Time (SPRT)
Chemical mechanical polishing (CMP)
Fabrication (FAB)
Days Per Mask Layer (DPML)
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/21495
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spelling my.unimap-214952012-10-21T08:11:27Z Analysis of optimum dispatching policies for semiconductor fabrication Mohd Azizi, Chik Uda, Hashim, Prof. Dr. Mohd_azizi@silterra.com First In First Out (FIFO) Shortest Processing Cycle Time (SPT) Critical Ratio (CR) Earliest Due Date (EDD) Shortest Remaining Processing Time (SPRT) Chemical mechanical polishing (CMP) Fabrication (FAB) Days Per Mask Layer (DPML) International Postgraduate Conference On Engineering (IPCE 2010), 16th - 17th October 2010 organized by Centre for Graduate Studies, Universiti Malaysia Perlis (UniMAP) at School of Mechatronic Engineering, Pauh Putra Campus, Perlis, Malaysia. This paper focuses on the comparison of the lot dispatching policies to reveal results for optimum product cycle time. The model is based on the 200mm-wafer size, 12K product Work In Progress (WIP), 10 product mixes in the current WIP with 2 new prototypes product start daily, and 3K-wafer start per week (WSPW) capacity. The dispatching policies to be compared are includes First In First Out (FIFO), Shortest Processing Time (SPT), Critical Ratio (CR), Earliest due date (EDD), Shortest Remaining Processing Time (SRPT) and Random (RAN). In the comparison, a snap shot of WIP of CMOS technology volume and product mix were taken at the wafer processing station from pad oxidation cleaning process to alloy. The result then is generated from the commercial simulation software, where requirements such as product processing time, manufacturing efficiency, equipment availability, WIP profile and product yield are the inputs for the model. The results reveal that CR dispatching policy gives the shortest cycle time for a product to complete all the processes of wafer fabrication steps compared to the other five dispatching policies by 5% to 13%. The results then enhanced and has been successfully accepted and realization in the real FAB operation. 2012-10-21T08:11:27Z 2012-10-21T08:11:27Z 2010-10-16 Working Paper 978-967-5760-03-7 http://hdl.handle.net/123456789/21495 en Proceedings of the International Postgraduate Conference on Engineering (IPCE 2010) Universiti Malaysia Perlis (UniMAP) Centre for Graduate Studies
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic First In First Out (FIFO)
Shortest Processing Cycle Time (SPT)
Critical Ratio (CR)
Earliest Due Date (EDD)
Shortest Remaining Processing Time (SPRT)
Chemical mechanical polishing (CMP)
Fabrication (FAB)
Days Per Mask Layer (DPML)
spellingShingle First In First Out (FIFO)
Shortest Processing Cycle Time (SPT)
Critical Ratio (CR)
Earliest Due Date (EDD)
Shortest Remaining Processing Time (SPRT)
Chemical mechanical polishing (CMP)
Fabrication (FAB)
Days Per Mask Layer (DPML)
Mohd Azizi, Chik
Uda, Hashim, Prof. Dr.
Analysis of optimum dispatching policies for semiconductor fabrication
description International Postgraduate Conference On Engineering (IPCE 2010), 16th - 17th October 2010 organized by Centre for Graduate Studies, Universiti Malaysia Perlis (UniMAP) at School of Mechatronic Engineering, Pauh Putra Campus, Perlis, Malaysia.
author2 Mohd_azizi@silterra.com
author_facet Mohd_azizi@silterra.com
Mohd Azizi, Chik
Uda, Hashim, Prof. Dr.
format Working Paper
author Mohd Azizi, Chik
Uda, Hashim, Prof. Dr.
author_sort Mohd Azizi, Chik
title Analysis of optimum dispatching policies for semiconductor fabrication
title_short Analysis of optimum dispatching policies for semiconductor fabrication
title_full Analysis of optimum dispatching policies for semiconductor fabrication
title_fullStr Analysis of optimum dispatching policies for semiconductor fabrication
title_full_unstemmed Analysis of optimum dispatching policies for semiconductor fabrication
title_sort analysis of optimum dispatching policies for semiconductor fabrication
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2012
url http://dspace.unimap.edu.my/xmlui/handle/123456789/21495
_version_ 1643793428344995840
score 13.214268

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