Design and analysis of Floating Point multiplier

• Main Author: Zariah Asari
• Other Authors: Nazuhusna Khalid (Advisor)
• Format: Learning Object
• Language: English
• Published: Universiti Malaysia Perlis 2008
• Subjects: Microprocessors; Floating-point multiplier; Microprogramming; Integrated circuits; Floating point unit; Multipliers
• Online Access: http://dspace.unimap.edu.my/xmlui/handle/123456789/1971

The most important floating-point representation is defined in IEEE Standard 754, adopted in 1985. This standard was developed to facilitate the portability of programs from one processor to another and to encourage the development of sophisticated, numerically all contemporary processors and arithmetic coprocessors. Floating-point operations are widely applied in scientific computations. With limited number of digits, the range and precision of the numbers represented by floating point systems can be improved. Most discussed are floating point addition, subtraction, multiplication and division. In discussing floating-point multiplication, by complies fully with the IEEE 754 Standard, the two mantissas are to be multiplied, and the two exponents are to be added. After the product calculated, the result is then normalized and rounded. Note that normalization could result in exponent underflow. The ANSI/IEEE Std 754-1985 standard for floating-point specifies that the implementation of a floating-point number consists of three bit fields; the first, a single bit, represents the sign. The next field holds the value of the exponent. The exponent value is a biased representation, specifically excess-127 for 32-bit floating-point (float). The last field is the significand which must be normalized within the range.