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Low power reconfigurable sub-band filter bank ASIC for MP3 decoder

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Main Authors: Gangamamba, B. P., Muralidhar, Pendyala V., Murthy, Nukala Satyanarayana
Other Authors: murthy@unimap.edu.my
Format: Article
Language:English
Published: Inderscience Publishers 2012
Subjects:
Low power reconfigurable pipelined architecture
MP3 decoder
Single precision multiplier
Synthesis filter banks
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/19136
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spelling my.unimap-191362012-05-13T01:53:25Z Low power reconfigurable sub-band filter bank ASIC for MP3 decoder Gangamamba, B. P. Muralidhar, Pendyala V. Murthy, Nukala Satyanarayana murthy@unimap.edu.my Low power reconfigurable pipelined architecture MP3 decoder Single precision multiplier Synthesis filter banks Link to publisher's homepage at http://www.inderscience.com/ There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results of MP3 algorithm on ARM processors, it has been observed that the synthesis filter bank in the audio decoder consumes maximum power. Hence, to reduce the power consumption of the filter bank, we developed an IEEE 754 single precision floating-point runtime reconfigurable architecture. The proposed architecture consumes less power at run time as the last 12 bits of the mantissa part of the synthesis filter coefficients are zero most of the time and, hence, the corresponding multipliers will be switched off. Since the active multipliers during inverse polyphase quadrature mirror filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesised and simulated the architecture using 0.35 m process technology under synopsys environment. A uniform worst case power reduction of 23.7% has been achieved in the frequency range from 1 MHz to 20 MHz when all the multipliers are in active state. 2012-05-13T01:53:25Z 2012-05-13T01:53:25Z 2009 Article International Journal of Information and Communication Technology, vol. 2 (1/2), 2009, pages 156-165 1466-6642 http://www.inderscience.com/offer.php?id=26438 http://hdl.handle.net/123456789/19136 en Inderscience Publishers
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Low power reconfigurable pipelined architecture
MP3 decoder
Single precision multiplier
Synthesis filter banks
spellingShingle Low power reconfigurable pipelined architecture
MP3 decoder
Single precision multiplier
Synthesis filter banks
Gangamamba, B. P.
Muralidhar, Pendyala V.
Murthy, Nukala Satyanarayana
Low power reconfigurable sub-band filter bank ASIC for MP3 decoder
description Link to publisher's homepage at http://www.inderscience.com/
author2 murthy@unimap.edu.my
author_facet murthy@unimap.edu.my
Gangamamba, B. P.
Muralidhar, Pendyala V.
Murthy, Nukala Satyanarayana
format Article
author Gangamamba, B. P.
Muralidhar, Pendyala V.
Murthy, Nukala Satyanarayana
author_sort Gangamamba, B. P.
title Low power reconfigurable sub-band filter bank ASIC for MP3 decoder
title_short Low power reconfigurable sub-band filter bank ASIC for MP3 decoder
title_full Low power reconfigurable sub-band filter bank ASIC for MP3 decoder
title_fullStr Low power reconfigurable sub-band filter bank ASIC for MP3 decoder
title_full_unstemmed Low power reconfigurable sub-band filter bank ASIC for MP3 decoder
title_sort low power reconfigurable sub-band filter bank asic for mp3 decoder
publisher Inderscience Publishers
publishDate 2012
url http://dspace.unimap.edu.my/xmlui/handle/123456789/19136
_version_ 1643792612208934912
score 13.160551

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