An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm

• Main Authors: Aznilnda, Zainodin, Aida Khairunisa, Ab. Kadir, M. Nasir, Ayob, Ahmad Fariz, Hasan, Amar Faiz, Zainal Abidin, Fazlinashatul Suhaidah, Zahid, Hazriq Izuan, Jafar, Ismail, Mohd Khairuddin
• Format: Article
• Language: English
• Published: 2014
• Subjects: TS Manufactures
• Online Access: http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf; http://umpir.ump.edu.my/id/eprint/7831/

Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmar...