Wavelet Transform Based Fault Identification and Reconfiguration for a Reduced Switch Multilevel Inverter Fed Induction Motor Drive

The multilevel inverter-based drive system is greatly affected by several faults occurring on switching elements. A faulty switch in the inverter can potentially lead to more losses, extensive downtime and reduced reliability. In this paper, a novel fault identification and reconfiguration process i...

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Bibliographic Details
Main Authors: Veerendra, A. S., A. A., Shah, Mohd Rusllim, Mohamed, Sekhar, Chavali Punya, Puiki, Leung
Format: Article
Language:English
Published: MDPI 2021
Subjects:
Online Access:http://umpir.ump.edu.my/id/eprint/31438/1/Wavelet%20Transform%20Based%20Fault%20Identification.pdf
http://umpir.ump.edu.my/id/eprint/31438/
https://doi.org/10.3390/electronics10091023
https://doi.org/10.3390/electronics10091023
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Summary:The multilevel inverter-based drive system is greatly affected by several faults occurring on switching elements. A faulty switch in the inverter can potentially lead to more losses, extensive downtime and reduced reliability. In this paper, a novel fault identification and reconfiguration process is proposed by using discrete wavelet transform and auxiliary switching cells. Here, the discrete wavelet transform exploits a multiresolution analysis with a feature extraction methodology for fault identification and subsequently for reconfiguration. For increasing the reliability, auxiliary switching cells are integrated to replace faulty cells in a proposed reduced-switch 5-level multilevel inverter topology. The novel reconfiguration scheme compensates open circuit and short circuit faults. The complexity of the proposed system is lower relative to existing methods. This proposed technique effectively identifies and classifies faults using the multiresolution analysis. Furthermore, the measured current and voltage values during fault reconfiguration are close to those under healthy conditions. The performance is verified using the MATLAB/Simulink platform and a hardware model.