Quality factor improvement of on-chip meander line resistor in high frequency operation / Wong Goon Weng

• Main Author: Wong , Goon Weng
• Format: Thesis
• Published: 2022
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://studentsrepo.um.edu.my/15321/1/Wong_Goon_Weng.pdf; http://studentsrepo.um.edu.my/15321/2/Wong_Goon_Weng.pdf; http://studentsrepo.um.edu.my/15321/

High-performance radio frequency integrated circuit (RFIC) applications are required in the rapidly growing microwave communication technology. Realising high-performance quality factor passive components at microwave frequencies have become challenging. The parasitic effect on the performance of the passive component draws the attention of manufacturers and researchers to the limiting RFIC application. On-chip resistors are embedded passive components that are widely used in the design of RFIC microelectronic circuits such as voltage-controlled oscillators, filters, and low noise amplifiers in electronic system-on-chip (SoC). The challenges in designing on-chip resistors included small package size, high-level integrity, reducing parasitic coupling effect, producing high resistivity and frequency stability with an acceptable low-quality factor operating at a high frequency. This thesis demonstrates an on-chip n-well meander line resistor configuration with higher sheet resistance, lower silicon area consumption and method design for improvement of Q factor over conventional straight lines on-chip resistor configuration. The on-chip n-well meander line resistors are designed and optimised for reducing the parasitic coupling effect with a low Q factor at less than 1.0 oscillate beyond 1 GHz frequency. Using a Sonnet 3D full-wave electromagnetic simulator, this thesis provides simulation analysis and validation for the proposed design on-chip meander line n-well resistors configuration. Three methods for improving on-chip meander line n-well resistor configuration with improved Q-factor performance were presented. The first DOE Factorial design method and the theoretical performance geometrical parameters of on-chip meander line n-well resistors were investigated. The simulation results showed that distance spacing increased and width widened with a decrease in parasitic capacitance coupling. Using the factorial design experiments DOE techniques, the optimised geometrical parameters configuration were achieved with a low-quality factor in 0.0713 at 1 GHz frequency, which improved by 94.02% compared to the conventional structure. The second additive method showed that the shielding ground conductor inserted into between segment n-well meander line reduced the parasitic capacitance coupling effect. Using a T-shaped shielding ground conductor with 2