Low power and low phase noise RF CMOS oscillators for wireless applications / Lim Chee Cheow

• Main Author: Lim , Chee Cheow
• Format: Thesis
• Published: 2019
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://studentsrepo.um.edu.my/11134/2/Lim_Chee_Cheow.pdf; http://studentsrepo.um.edu.my/11134/1/Lim_Chee_Cheow.pdf; http://studentsrepo.um.edu.my/11134/

The insatiable demand for global connectivity due to the exponential increase in the number of wirelessly connected portable devices has motivated the researchers from both academia and industries to incessantly improve the system performance in terms of faster data rate, lower power consumption at lower cost. Thus, design of LC-oscillators becomes ever challenging, as it is one of the crucial building blocks in the modern RF communication systems to underpin data (de)modulation. Yet, oscillator phase noise imposes bottleneck to the overall radio performance. Therefore, two LC-oscillator architectures are proposed in this work. The first one is the inverse-class-F (class-F-1) oscillator, featuring a single-ended PMOS-NMOS complementary architecture capable of generating differential output and a step-up transformer-based two-port resonator capable of 1) boosting the drain-to-gate voltage gain and 2) achieving two high-Q-resonances at two impedance peaks of fLO and 2fLO concurrently. This shapes the drain voltage of the –gm transistors into a half-sinusoidal waveform which extends the flat span of the minimum impulse sensitivity function (ISF). The voltage gain reduces the current commutation time, thereby suppressing the transistor’s noise-to-phase noise conversion. Fabricated in 65-nm CMOS, the prototype measures a phase noise of –144.8 dBc/Hz at 10 MHz offset while oscillating at 4 GHz. With a reasonable tuning range of 3.49-to-4.51 GHz (25.5%), the proposed class-F-1 oscillator consumes only 1.14-to-1.2 mW at a supply of 0.6V, corresponding to a Figure-of-Merit (FoM) of 195.6-to-196.2 dBc/Hz. The second work, class-C Mode-Switching Single-Ended Complementary (MS-SEC) oscillator aims to break the trade-off between oscillator’s power consumption and frequency tuning range while achieving low phase noise. It utilises mode switching technique, allowing the dual-core oscillators with stacked PMOS-NMOS –gm transistors to operate in class-C mode by delivering tall and narrow current pulses to achieve a better current efficiency and to lower the noise contribution of the –gm transistors. Prototyped in 130-nm CMOS, measurement result shows the MS-SEC oscillator meets the stringent phase noise specification of the SAW-less GSM standard while consuming only 5.1-to-7.3 mW at a supply of 1.2 V and covering 2.4-to-5 GHz (70.6% tuning range), corresponding to FoM of >190 dBc/Hz throughout the tuning range.