Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count

This paper presented an improved asymmetrical multilevel inverter module with reduced switches count. The basic module is capable of producing 15 level outputs with four dc sources and 10 switches. The proposed topology has an inherent ability to generate negative voltage levels, made it possible to...

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Main Authors: Arif, M. Saad Bin, Sarwer, Zeeshan, Siddique, Marif Daula, Md. Ayob, Shahrin, Iqbal, Atif, Mekhilef, Saad
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Published: John Wiley & Sons 2021
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Online Access:http://eprints.um.edu.my/28232/
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spelling my.um.eprints.282322022-03-05T02:17:58Z http://eprints.um.edu.my/28232/ Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count Arif, M. Saad Bin Sarwer, Zeeshan Siddique, Marif Daula Md. Ayob, Shahrin Iqbal, Atif Mekhilef, Saad T Technology (General) TA Engineering (General). Civil engineering (General) This paper presented an improved asymmetrical multilevel inverter module with reduced switches count. The basic module is capable of producing 15 level outputs with four dc sources and 10 switches. The proposed topology has an inherent ability to generate negative voltage levels, made it possible to utilize lower rating switches, and has lower total standing voltage. To have more number of levels, a series-connected cascade extension of the module has been done. The three different algorithms for selecting the magnitude of dc sources are proposed. The generalized relations for different parameters are based on the number of added basic units and the number of presented levels for each source selection algorithm. Nearest level control (NLC) is used as the modulation technique. A comparative study shows that the developed topology outperformed other selected existing topologies on many parameters. The performance of the module is evaluated through detailed simulation and power loss analysis. Accuracy of the obtained simulation results is validated through proper experimental testing of the circuit in the laboratory. John Wiley & Sons 2021-06 Article PeerReviewed Arif, M. Saad Bin and Sarwer, Zeeshan and Siddique, Marif Daula and Md. Ayob, Shahrin and Iqbal, Atif and Mekhilef, Saad (2021) Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count. International Journal of Circuit Theory and Applications, 49 (6). pp. 1757-1775. ISSN 0098-9886, DOI https://doi.org/10.1002/cta.2971 <https://doi.org/10.1002/cta.2971>. 10.1002/cta.2971
institution Universiti Malaya
building UM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaya
content_source UM Research Repository
url_provider http://eprints.um.edu.my/
topic T Technology (General)
TA Engineering (General). Civil engineering (General)
spellingShingle T Technology (General)
TA Engineering (General). Civil engineering (General)
Arif, M. Saad Bin
Sarwer, Zeeshan
Siddique, Marif Daula
Md. Ayob, Shahrin
Iqbal, Atif
Mekhilef, Saad
Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
description This paper presented an improved asymmetrical multilevel inverter module with reduced switches count. The basic module is capable of producing 15 level outputs with four dc sources and 10 switches. The proposed topology has an inherent ability to generate negative voltage levels, made it possible to utilize lower rating switches, and has lower total standing voltage. To have more number of levels, a series-connected cascade extension of the module has been done. The three different algorithms for selecting the magnitude of dc sources are proposed. The generalized relations for different parameters are based on the number of added basic units and the number of presented levels for each source selection algorithm. Nearest level control (NLC) is used as the modulation technique. A comparative study shows that the developed topology outperformed other selected existing topologies on many parameters. The performance of the module is evaluated through detailed simulation and power loss analysis. Accuracy of the obtained simulation results is validated through proper experimental testing of the circuit in the laboratory.
format Article
author Arif, M. Saad Bin
Sarwer, Zeeshan
Siddique, Marif Daula
Md. Ayob, Shahrin
Iqbal, Atif
Mekhilef, Saad
author_facet Arif, M. Saad Bin
Sarwer, Zeeshan
Siddique, Marif Daula
Md. Ayob, Shahrin
Iqbal, Atif
Mekhilef, Saad
author_sort Arif, M. Saad Bin
title Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
title_short Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
title_full Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
title_fullStr Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
title_full_unstemmed Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
title_sort asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count
publisher John Wiley & Sons
publishDate 2021
url http://eprints.um.edu.my/28232/
_version_ 1735409546119086080
score 13.160551