High-Speed shortest path co-processor design

• Main Authors: Idris, Mohd Yamani Idna, Abu Bakar, Suraya, Tamil, Emran Mohd, Razak, Zaidi, Noor, Noorzaily Mohamed
• Format: Conference or Workshop Item
• Published: 2009
• Subjects: QA75 Electronic computers. Computer science
• Online Access: http://eprints.um.edu.my/2287/; https://ieeexplore.ieee.org/document/5072059

Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware approach which implements FPGA technology to find the shortest path between two nodes. The FPGA approach will demonstrate how parallelism can be used to significantly reduce calculation steps compared to sequential effort. In this paper, A-Star algorithm has been chosen for the shortest path calculation since it can achieve superior time running based on its heuristic behavior.