Performance analysis of full adders in CIC decimation filter / Yeoh Poay Zheng and L. Lee

• Main Authors: Zheng, Yeoh Poay, Lee, L.
• Format: Article
• Language: English
• Published: 2018
• Subjects: Detectors. Sensors. Sensor networks
• Online Access: https://ir.uitm.edu.my/id/eprint/86394/1/86394.pdf; https://ir.uitm.edu.my/id/eprint/86394/; https://e-ajuitmct.uitm.edu.my/v3/

This article presents analysis of various full adder architecture on Cascaded Integrator-Comb (CIC) filter of delta-sigma ADC. The structure of CIC filter consists of an integrator and a differentiator stage that is built from a cascaded full adder and delay element. Since each of the element within CIC filter has its own low-power architecture, full adder is one of the block that consumes huge amount of power compared to others. In this paper, four different type of full adder’s architecture is designed and simulated with CIC decimation filter. There are 28T conventional, pseudo-NMOS adder, 16T hybrid adder and modified 14T hybrid adder. The performance parameters such as delay, total power dissipation and power delay product (PDP) of CIC filter were compared. This analysis shows that 16T hybrid full adder CIC filter has reduced up to 38.15% of power consumption and 39.18% of power product delay compared to conventional adder. Hence, a complete 1-bit third order of 16T hybrid adder CIC filter is implemented with size area of 118.23μm × 22.38μm.