Hardware design of convolutional encoder and decoder for digital communication system / Sayed Aziz Sayed Hussin
This paper focused on Convolutional Codes as one of the error detection and correction technique that use special generator polynomial. The first generator polynomial is X3 +X*+ X1 + 1 (1111) and the second generator polynomial is X3 + X2 + 1 (1011). The simulation is performing using Circuit Maker...
Saved in:
Main Author: | Sayed Hussin, Sayed Aziz |
---|---|
Format: | Thesis |
Language: | English |
Published: |
2003
|
Subjects: | |
Online Access: | https://ir.uitm.edu.my/id/eprint/68030/1/68030.pdf https://ir.uitm.edu.my/id/eprint/68030/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Implementation of convolutional encoder and Viterbi decoder using VHDL
by: Wong, Yin Sweet, et al.
Published: (2009) -
Developed convolutional encoder and viterbi decoder using c+
by: Chin Toong Hing
Published: (2023) -
Design and fabricate universal hook for car usage / Sayed Saqif Iman Sayed Safari
by: Sayed Safari, Sayed Saqif Iman
Published: (2022) -
Multi-attention bottleneck for gated convolutional encoder-decoder-based speech enhancement
by: Saleem, Nasir, et al.
Published: (2023) -
An overview of Stuart Hall’s encoding and decoding theory with film communication
by: Yuting, Xie, et al.
Published: (2022)