Enhancing submicron CMOS device performance / Rosfariza Radzali, Wan Fazlida Hanim Abdullah and Ibrahim Ahmad.

• Main Authors: Radzali, Rosfariza, Abdullah, Wan Fazlida Hanim, Ahmad, Ibrahim
• Format: Research Reports
• Language: English
• Published: 2007
• Subjects: Electronics; Apparatus and materials; Semiconductors
• Online Access: http://ir.uitm.edu.my/id/eprint/42338/1/42338.PDF; http://ir.uitm.edu.my/id/eprint/42338/

Semiconductor revolution has been possible with the downsizing or scaling the size of semiconductor devices such as Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Scaling of MOSFET becomes very important in Ultra Large- Scale Integration (ULSI) for high integration and high speed operation. In this dissertation, a study has been done for development of 0.13 pm CMOS technology. The device design, fabrication process and characterization have been discussed. By using the scaling rules, a Complementary Metal Oxide Semiconductor (CMOS) transistor with channel size of 0.13pm has been scaled down from a CMOS transistor with channel size of 0.18 pm that had been designed and fabricated before. In order to achieve the desire electrical characteristic of 0.13pm CMOS transistor, several parameters have to be scaled such as channel gate length, gate oxide thickness, ion implantation for threshold voltage adjustment and other related specifications. Scaling limiting factors such as short channel effect and hot electron effect have been given much consideration by implementing lightly doped drain (LDD) structure and shallow junction of drain/source. Shallow Trench Isolation (STI) has been proposed for the isolation technique to eliminate the oxidation encroachment or bird’s beak by Local Oxidation of Silicon (LOCOS). Silicide using cobalt silicide has been implemented to reduce the sheet resistance and the double metal gate for better performance. The stress analysis between the STI and LOCOS isolation technique has been done and LOCOS structure introduce more stress if compare to the STI structure. Fabrication and simulation of the CMOS transistor is done by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools. NMOS and PMOS were simulated individually to simplify the fabrication process and shorten the simulation time. From the simulation results, the threshold voltage for nMOS and pMOS are 0.359863V and -0.335567V respectively. As to define the functionality of 0.13pm CMOS transistor, the relation of Id - Vj and I d - Vg are presented