Comparative study on different type of multiplier in verilog HDL: article / Nik Ahmad Afnan Nik Azman

• Main Author: Nik Azman, Nik Ahmad Afnan
• Format: Article
• Language: English
• Published: 2018
• Subjects: Computer engineering. Computer hardware
• Online Access: https://ir.uitm.edu.my/id/eprint/105134/2/105134.pdf; https://ir.uitm.edu.my/id/eprint/105134/

This paper presents the comparative study on different type of multiplier in Verilog HDL. Multiplier is one of the most important components in digital design system and embedded applications. This research study on the different type of multiplier on the algorithm, implementation on verilog and performance analysis. Today researches already creates so many type of multiplier. This paper helps by doing comparative study of some of this multiplier for future references; Three type of multiplier used in this comparative study, that are Array, Vedic and Wallace with variation of 4-bits and 8-bits. This technical paper deals with design, synthesis and simulation using Quartus II and Modelsim. The performance of the multipliers is based on the power and area. Quartus II used to check the wire connectivity in logic and module of the design. To check the validity and functionality of the multiplier, Modelsim software are used. The same input data is used on each multiplier because it is expected to get the same output. In this study, it shows that the performance of multiplier are depending on it algorithm. The algorithm of multiplier help the design become more better in performance of power and area when the number of bits changed.