Analysis and optimization of 3 to 5 GHz CMOS low noise amplifier for ultra-wideband system / Khairul Anuar Abdullah
This project presents an analysis for single stage Ultra-wideband CMOS Low Noise Amplifier interfacing interstage matching inductor cascade inductive source degeneration. Cadence SpectraRF design tool is used in the analysis and to optimize the simulation gain and noise performance base on transisto...
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| Format: | Thesis |
| Language: | English |
| Published: |
2010
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| Online Access: | https://ir.uitm.edu.my/id/eprint/102756/1/102756.pdf https://ir.uitm.edu.my/id/eprint/102756/ |
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| Summary: | This project presents an analysis for single stage Ultra-wideband CMOS Low Noise Amplifier interfacing interstage matching inductor cascade inductive source degeneration. Cadence SpectraRF design tool is used in the analysis and to optimize the simulation gain and noise performance base on transistor size and inductor. The LNA was analysed using Siltera 0.18μm CMOS technology for a 3 to 5 GHz ultrawideband system. By carefully optimization of the size of transistor and inductor, it can increase the overall broadband gain while maintaining a low level of noise figure. The LNA UWB achieved stability factor’s more than 1, power gain +11.27dB and noise figure of 2.15 dB at frequency 4.5GHz. For the S-parameter analysis the bandwidth is 2.8 – 5.1 GHz with input (S11) and output matching (S22) below than -2.25 dB and -1.4 dB respectively. |
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