The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology

• Main Authors: Yusop, N. S., Nordin, Anis Nurashikin, Khairi, M. Azim, Hasbullah, Nurul Fadzlin
• Format: Article
• Language: English; English; English
• Published: Taylor & Francis 2018
• Subjects: TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices
• Online Access: http://irep.iium.edu.my/69761/19/69761%20The%20impact%20of%20scaling%20on%20single%20event%20upset%20in%206T%20and%2012T.pdf; http://irep.iium.edu.my/69761/2/69761_The%20impact%20of%20scaling%20on%20single%20event%20upset_scopus.pdf; http://irep.iium.edu.my/69761/25/69761_wos.pdf; http://irep.iium.edu.my/69761/; https://www.tandfonline.com/doi/abs/10.1080/10420150.2018.1542695

As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error in the transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 130 up to 22 nm CMOS technology towards SEU. Besides that, this paper discusses the trend of critical linear energy transfer (LET) and collected charge due to technology scaling for the respective circuit. The critical LET (LETcrit) and critical charge (Qcrit) of 6T are approximately 50% lower compared with 12T SRAMs.