Power analysis with variable traffic loads for next generation interconnection networks

• Main Authors: Faisal, Faiz Al, Rahman, M.M. Hafizur, Inoguchi, Yasushi
• Format: Conference or Workshop Item
• Language: English; English
• Published: IEEE 2016
• Subjects: TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices; TK7885 Computer engineering
• Online Access: http://irep.iium.edu.my/53589/1/53589_Power%20analysis%20with%20variable%20traffic%20loads%20for%20next%20generation.pdf; http://irep.iium.edu.my/53589/2/53589_Power%20analysis%20with%20variable%20traffic%20loads%20for%20next%20generation_Scopus.pdf; http://irep.iium.edu.my/53589/; http://ieeexplore.ieee.org/abstract/document/7828408/

Power consumption is the most important factor for the consideration of next generation supercomputers. In addition, the requirement of power usages can be even scaled up to more than 300MW (which is nearly equal to the one nuclear power plant) with the conventional networks. On the other hand, hierarchical interconnection networks can be a possible solution to those issues. 3D-TTN is a hierarchical interconnection network where lowest level is configured as the 3Dtorus network, following the 2Dtorus network at the higher-level networks. The main focus for this paper is the power analysis with variable traffic load along with the fault tolerance, cost, packing density and message traffic density of 3D-TTN comparing against various other networks. In our early research, 3D-TTN has achieved near about 21% better diameter performance, 12% better average distance performance and eventually required about 32.48% less router power usage at the lowest level than the 5Dtorus network for 1% traffic load. This paper shows the power comparison with the router and link power rather than considering the router power only. Our analysis shows that 3DTTN will require about 39.96% less router and link power than the 5Dtorus network for 10% traffic. With 30% traffic load, 3DTTN will require about 38.42% less power than the 5Dtorus network for the on-chip network. Even considering some topological parameters, 3D-TTN could also achieve some desirable performance by comparing other networks.