Development of a low cost lapping process
Conventional process of producing silicon based products uses large work-piece and it is difficult to attain high flatness of the finished surface. Thus it is not unusual to find it difficult to fine finish small area of planar surfaces and attain high degree of flatness on the finished surfaces. Th...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/17035/1/Paper_ID770.pdf http://irep.iium.edu.my/17035/ http://www.iium.edu.my/ampt2009/date.htm |
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| Summary: | Conventional process of producing silicon based products uses large work-piece and it is difficult to attain high flatness of the finished surface. Thus it is not unusual to find it difficult to fine finish small area of planar surfaces and attain high degree of flatness on the finished surfaces. The manufacturing of silicon wafers in particular involves numerous grinding, lapping, and polishing processes of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making IC chips especially, it is difficult to lap and/polish the substrate and obtain low surface integrity, surface finish and at the same time generate flat planar surfaces. Therefore the understanding of lapping process is very essential for economic manufacture and process improvement of thin silicon chips. A low cost lapping process has been developed, the process tried out on thin silicon chips that generated damage-free with a mirror-like surfaces of low roughness values and reasonably high degree of flatness. |
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