DOWNSCALING OF 0.25uM TO O.13uM NMOS USING SILVACO SOFTWARE WITH DIFFERENT SUBMICRON TECHNOLOGY

• Main Author: MOHD SUPIAN, NORLIZA
• Format: Final Year Project
• Language: English
• Published: Universiti Teknologi PETRONAS 2007
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://utpedia.utp.edu.my/9513/1/2007%20-%20Downscaling%20of%200.25yM%20to%200.13yM%20NMOS%20using%20Silvaco%20Software%20with%20Different%20Submicron%20Techn.pdf; http://utpedia.utp.edu.my/9513/

For the last three decades, MOS device technologies have been improved due to downscaling. It consumes less power, have shorter delay and occupy less space. The CMOS comprises of p-type and n-type, has become the main growth of miniaturization microelectronics industry. In this project, ATHENA andATLAS are simulators used with the objective to downscale 0.25um to 0.13um NMOS using two different recipes and to obtain its electrical characteristic. Ascaling factor, a of 1.923 is utilized. Three factors are investigated; the gate length (Lg), gate oxide thickness (U) and threshold voltage (Vth) adjust implant. The parameters evaluated include W, Vth and saturation current (WO as well as ID-VD, Id-Vg and subthreshold current (St) curve. After downscaling to 0.13um, both recipes haveWvalues of3.36nm while the Vth obtain are 0.31V and 0.37V respectively. The W value is 343uA/um and 519uA/um while the St is 65mV/dec and 128mV/dec respectively. Each recipe has its own drawback. First recipe has lower Id^ and lower St while second recipe has higher IDsat and higher St Higher W means the device can perform at taster speed while lower St. shows the device has good turn-off characteristics. Overall, the electrical parameters obtained are agreeable with ITRS requirement and other reported works except for the result ofW This could be due to the direct scaling. Other parameters such as St could not be compared as itis confidential to the public.