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DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP

In this report, CMOS 0-latch with and without open faults are designed. Schematics and layout are simulated using Cadence Spectre. The process parameter used in design is Technology AMJ06. The results obtained from the simulation are observed for both cases (with open and without open fault). It...

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Main Author: MOHAMMAD, MARLIANA
Format: Final Year Project
Language:English
Published: Universiti Teknologi Petronas 2008
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://utpedia.utp.edu.my/7139/1/2008%20-%20Design-for-test%20ability%20%28DFT%29%20technique%20for%20open%20faults%20in%20cmos%20latchflip-flop.pdf
http://utpedia.utp.edu.my/7139/
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spelling my-utp-utpedia.71392017-01-25T09:45:02Z http://utpedia.utp.edu.my/7139/ DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP MOHAMMAD, MARLIANA TK Electrical engineering. Electronics Nuclear engineering In this report, CMOS 0-latch with and without open faults are designed. Schematics and layout are simulated using Cadence Spectre. The process parameter used in design is Technology AMJ06. The results obtained from the simulation are observed for both cases (with open and without open fault). It is proven that there are certain open locations in CMOS 0-latch could not be detected instantly. This is where the purpose of designing the OFT comes in. OFT circuitry is added to the 0-Jatch to create voltage competition in the circuit. With OFT circuitry implemented in the 0- latch, the open fault can be detected easily. From observation, the output at the memory state is flipped during testing. The layout for 0-latch with added OFT circuitry is also included. Universiti Teknologi Petronas 2008-06 Final Year Project NonPeerReviewed application/pdf en http://utpedia.utp.edu.my/7139/1/2008%20-%20Design-for-test%20ability%20%28DFT%29%20technique%20for%20open%20faults%20in%20cmos%20latchflip-flop.pdf MOHAMMAD, MARLIANA (2008) DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP. Universiti Teknologi Petronas. (Unpublished)
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Electronic and Digitized Intellectual Asset
url_provider http://utpedia.utp.edu.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
MOHAMMAD, MARLIANA
DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
description In this report, CMOS 0-latch with and without open faults are designed. Schematics and layout are simulated using Cadence Spectre. The process parameter used in design is Technology AMJ06. The results obtained from the simulation are observed for both cases (with open and without open fault). It is proven that there are certain open locations in CMOS 0-latch could not be detected instantly. This is where the purpose of designing the OFT comes in. OFT circuitry is added to the 0-Jatch to create voltage competition in the circuit. With OFT circuitry implemented in the 0- latch, the open fault can be detected easily. From observation, the output at the memory state is flipped during testing. The layout for 0-latch with added OFT circuitry is also included.
format Final Year Project
author MOHAMMAD, MARLIANA
author_facet MOHAMMAD, MARLIANA
author_sort MOHAMMAD, MARLIANA
title DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
title_short DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
title_full DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
title_fullStr DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
title_full_unstemmed DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
title_sort design-for-testability (dft) technique for open faults in cmos latch/flip-flop
publisher Universiti Teknologi Petronas
publishDate 2008
url http://utpedia.utp.edu.my/7139/1/2008%20-%20Design-for-test%20ability%20%28DFT%29%20technique%20for%20open%20faults%20in%20cmos%20latchflip-flop.pdf
http://utpedia.utp.edu.my/7139/
_version_ 1739831425834680320
score 13.160551

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