Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology

The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in two t...

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Main Author: Mastura binti Omar, Mastura
Format: Final Year Project
Published: Universiti Teknologi Petronas 2009
Subjects:
Online Access:http://utpedia.utp.edu.my/1576/
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spelling my-utp-utpedia.15762017-01-19T15:48:34Z http://utpedia.utp.edu.my/1576/ Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology Mastura binti Omar, Mastura TK Electrical engineering. Electronics Nuclear engineering The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in two transistor of tracking circuit directly contribute to the latch delay. The fundamental of this project is to understand the basic operation of CML of D Flip-flop based frequency divider. Universiti Teknologi Petronas 2009 Final Year Project NonPeerReviewed Mastura binti Omar, Mastura (2009) Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology. Universiti Teknologi Petronas. (Unpublished)
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Electronic and Digitized Intellectual Asset
url_provider http://utpedia.utp.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Mastura binti Omar, Mastura
Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology
description The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in two transistor of tracking circuit directly contribute to the latch delay. The fundamental of this project is to understand the basic operation of CML of D Flip-flop based frequency divider.
format Final Year Project
author Mastura binti Omar, Mastura
author_facet Mastura binti Omar, Mastura
author_sort Mastura binti Omar, Mastura
title Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology
title_short Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology
title_full Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology
title_fullStr Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology
title_full_unstemmed Design Common Mode Logic (CML) Frequency Divider In CMOS Process Technology
title_sort design common mode logic (cml) frequency divider in cmos process technology
publisher Universiti Teknologi Petronas
publishDate 2009
url http://utpedia.utp.edu.my/1576/
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score 13.188404