RISC-V instruction set extension on blockchain application
This project is an instruction set extension project based on RISC-V architecture for academic purpose. Blockchain technology was widely used today to keep records due to its high security and reliability. However, blockchain required a high computing power to function. Although there were numero...
Saved in:
Main Author: | |
---|---|
Format: | Final Year Project / Dissertation / Thesis |
Published: |
2024
|
Subjects: | |
Online Access: | http://eprints.utar.edu.my/6486/1/fyp_CT_2024_CKS.pdf http://eprints.utar.edu.my/6486/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Summary: | This project is an instruction set extension project based on RISC-V architecture for academic
purpose. Blockchain technology was widely used today to keep records due to its high security
and reliability. However, blockchain required a high computing power to function. Although
there were numerous ways to improve the performance speed of blockchain technology in
software implementations, hardware implementation of the blockchain algorithms was a more
preferred choice due to the emerging open-source computer architecture, RISC-V. RISC-V was
free and open license for anyone to customize their IC design. By adding new instruction
extensions to the RISC-V cores, they could be specialized to run certain types of tasks. This
would greatly shorten the instructions used by the algorithms and improved the execution time
of the programmes. One of the most common cryptographic algorithms used in blockchain
would be selected in this paper, typically djb2 hash algorithm. In this project, some instructions
were proposed to execute the cryptographic algorithm in shorter clock cycles and shorter
execution time. Towards the end of the project, the algorithms would be executed in a base
RISC-V core and an extended RISC-V core using simulation tools to perform performance
analysis. The simulation tool used in this project was Chipyard, which is a one-stop
development tool for anything regarding RISC-V customization. One of the main components
in Chipyard was Spike simulator, which was a software simulation tool in RISC-V standards
to execute the software executable file and also output the hardware information used during
the execution. Spike was used to run the compiled source codes in C/C++ language to
determine the execution time and clock cycles used by the programme. A RISC-V GNU
toolchain was installed for the compilation of the programme. The toolchain was also
customised and extended with extra instructions to compile the programme. The compiled
programme was simulated in Spike ISA simulator to test with the extension and without the
extension. The results were presented at the end of the report. |
---|