Toolchain development and queue system enhanced security coprocessor for FPGA-based internet of things (IoT) processor

• Main Author: See, Jin Chuan
• Format: Final Year Project / Dissertation / Thesis
• Published: 2019
• Subjects: QA75 Electronic computers. Computer science; QA76 Computer software
• Online Access: http://eprints.utar.edu.my/4412/1/CEA%2D2019%2D1705149%2D1.pdf; http://eprints.utar.edu.my/4412/

Internet of Things (IoT) is developing by leaps and bounds in recent years, which opens up many interesting applications that potentially revolutionize our daily life. Many IoT processors and sensor node designs are being proposed in recent years for various applications, including those designed based on microcontroller, ASIC and FPGA. A recently proposed FPGA based IoT processor, RISC32, is one of the notable examples that provide flexible configurability to meet the needs in IoT applications. However, it does not come with compilation toolchain that support high level language, which increases the code development time. On top of that, one of the main reasons that limit the widespread adoption of IoT in many fields, is the lack of security feature. For instance, failure to provide data confidentiality could cause information leak and bring losses to the users. Unfortunately, RISC32 does not support encryption capability in hardware. In view of that, this research work aims to improve RISC32 in two aspects: providing compilation toolchain in C language and introduce hardware core to perform encryption. The most commonly used encryption scheme, Advanced Encryption System (AES) was used in this research work. While AES could be effectively implemented in software, the performance is slow, at the same time affecting the energy efficiency and responsiveness of IoT sensor node. This research work implemented AES as a coprocessor to RISC32 to speed up the encryption process. Experimental result shows at least 200x speed-up and ~99% energy reduction achieved by the AES coprocessor, compared to the software implementation. However, the RISC32 processor has to wait for AES core to complete the encryption before proceeding with other operations, due to data dependency. Hence, a novel Queue System is proposed to overlap the encryption operation with sampling of data, which follows the typical IoT software pattern. Further 1.48x speed-up and ~19% energy reduction was achieved with the introduction of Queue System. To enable rapid IoT application development on RISC32, this research work also delivers a compilation toolchain for RISC32 based on retargetable compiler framework, LLVM. By utilizing the existing MIPS Backend, the LLVM is extended to support code generation for RISC32. The compilation toolchain enables development option using C language on RISC32, where it was previously restricted to slow and error prone assembly language development option. The achievement obtained in this research work is beneficial to IoT applications, which emphasize on performance and energy consumption. The proposed Queue System can be used by other processor architectures to efficiently integrate with another block cipher coprocessor. On the other hand, the developed LLVM compilation toolchain can also allow easy extension of additional coprocessors to the RISC32 IoT processor.