Design and implementation of a SPI controller for zigbee module

• Main Author: Yong, Min An
• Format: Final Year Project / Dissertation / Thesis
• Published: 2020
• Subjects: T Technology (General); TA Engineering (General). Civil engineering (General)
• Online Access: http://eprints.utar.edu.my/3830/1/16ACB01733_FYP.pdf; http://eprints.utar.edu.my/3830/

This project is about the 4-wire Serial Peripheral Interface (SPI) controller unit design and implementation for academic purpose. The development of this project will begin with the design of the SPI controller unit. The RTL design flow will be used throughout the project development and the micro-architectural level design will be focused more as the SPI controller to be designed is in the unit level. The internal blocks of the SPI controller unit will be modeled by using Verilog HDL before they are integrated into unit level. The specifications of the SPI controller unit and its internal block will be functionally verified by writing testbenches in Verilog HDL. After the SPI controller unit has been functionally verified, it will be integrated into the existing RISC32 pipelined processor developed in UTAR. This involves the development of the interface between the SPI controller and the RISC32 based on I/O memory mapping technique. Moving on, an Interrupt Service Routine (ISR) will be specifically developed and implemented on the RISC32 for handling the data received by the SPI controller. A MIPS test program will also be written to test the correctness of the ISR functionalities. Lastly, it will be synthesized on the Field Programmable Gate Array (FPGA) technology and further interfaced with CC2420 RF transceiver in this project for wireless data communication. The CC2420 will be configured as the slave device whereas the SPI controller unit will be used as the master device. Data communication between the SPI controller unit in the RISC32 pipelined processor and the CC2420 RF transceiver is performed via a simple 4-wire SPI compatible interface (MOSI, MISO, SCLK and SS pin). In short, a piece of software, stimulation result and hardware are expected to be delivered at the end of the project.