A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure

• Main Authors: Muhazam Mustapha,, Jeffery Lee,, Anis Shahida Niza Mokhtar,, Kamarul ‘Asyikin Mustafa,, Bakhtiar Affendi Rosdi,
• Format: Article
• Language: English
• Published: Penerbit Universiti Kebangsaan Malaysia 2021
• Online Access: http://journalarticle.ukm.my/19093/1/13.pdf; http://journalarticle.ukm.my/19093/; https://www.ukm.my/jkukm/si-42-2021/

The current CMOS’s industry standard XOR and XNOR gate consist of 12 and 10 transistors, respectively. This transistor count could be lowered down to produce low power circuits as XOR/XNOR are extensively used in many functional modules. As a solution, a method for realizing low transistor count XOR/XNOR gates using a special property of symmetric Boolean function is proposed. This property suggests that the circuits for such functions can be realized with fewer transistors using a special lattice structure circuit. Modifications are made to the original lattice structure to match with the current CMOS technology requirements. The final circuits require eight transistors each for XOR/XNOR with mixtures of NMOS and PMOS at push-up and pull-down networks. Simulations show that the intended logic functions of XOR/XNOR are achieved. The reading of actual voltage swing, however, shows that the output is either 0.3 V over ground or below VDD when there is a mixture of NMOS and PMOS as pull-down or push-up networks, respectively. More voltage loss of 0.4 V is observed if only NMOS is at push-up or only PMOS is at pull-down networks. As a preliminary work, this achievement of the functional logic level warrants more future work to improve the loss in output voltage swing.