High Speed Numerical Integration Algorithm Using FPGA
Conventionally, numerical integration algorithm is executed in software and time consuming to accomplish. Field Programmable Gate Arrays (FPGAs) can be used as a much faster, very efficient and reliable alternative to implement the numerical integration algorithm. This paper proposed a hardware imp...
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| 主要な著者: | , , , , , |
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| フォーマット: | 論文 |
| 出版事項: |
2017
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| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/id/eprint/81129/ http://dx.doi.org/10.4314/jfas.v9i4S.7 |
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| 要約: | Conventionally, numerical integration algorithm is executed in software and time consuming to accomplish. Field Programmable Gate Arrays (FPGAs) can be used as a much faster, very efficient and reliable alternative to implement the numerical integration algorithm. This paper proposed a hardware implementation of four numerical integration algorithms using FPGA. The computation is based on Left Riemann Sum (LRS), Right Riemann Sum (RRS), Middle Riemann Sum (MRS) and Trapezoidal Sum (TS) algorithms. The system performance is evaluated based on target chip Altera Cyclone IV FPGA in the metrics of resources utilization, clock latency, execution time, power consumption and computational error compared to the other algorithms. The result also shows execution time of the FPGA are much faster compared to the software implementation. |
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