Low Power Standard Cell Library Design For Application Specific Integrated Circuit
With the expansion of portable and wireless electronics product in the current market demand, the focus of designing VLSI system has shifted from high speed to low power domain. This requires chip designers to minimize power consumption at all design level such as system, algorithm, architecture,...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English English |
| 出版: |
2002
|
| 主題: | |
| 在線閱讀: | http://psasir.upm.edu.my/id/eprint/12086/1/FK_2002_52.pdf http://psasir.upm.edu.my/id/eprint/12086/ |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 總結: | With the expansion of portable and wireless electronics product in the current
market demand, the focus of designing VLSI system has shifted from high speed to
low power domain. This requires chip designers to minimize power consumption at
all design level such as system, algorithm, architecture, circuit and technology.
The objective of this work is to develop low power CMOS standard cell
library to be used in application specific integrated circuit (ASIC) design flow. The
design methodology focuses on all aspect of circuit design: transistor size, logic
style, layout style, cell topology, and circuit design for minimum power
consumption. The standard cell library is targeted for general-purpose application,
especially in microprocessor design. For rapid design implementation, the library is
designed to be used together with the commercial logic synthesis and automatic cell
placement and routing tools. Results show that the microprocessor targeted to the
low power library gives 44% power saving compared to the conventional library,
with both designs operate at the same clock frequency of 50MHz. |
|---|