Voltage balancing in DC link capacitor for seven level cascaded multilevel inverter
Multilevel inverters enables implementation of high-power-medium-voltage applications using smaller rated devices resulting to cheaper and compact design. Currently, researchers are interested in developing distributed generation (DG) with multilevel topology that produces not just active power dema...
保存先:
| 主要な著者: | , |
|---|---|
| フォーマット: | 論文 |
| 言語: | en_US |
| 出版事項: |
2017
|
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 要約: | Multilevel inverters enables implementation of high-power-medium-voltage applications using smaller rated devices resulting to cheaper and compact design. Currently, researchers are interested in developing distributed generation (DG) with multilevel topology that produces not just active power demands, but also incorporated with custom power capabilities for power quality improvement. However, multilevel inverters are susceptive to voltage unbalance at the DC link capacitor which affects the output voltages. For this reason, a voltage balancing method is presented for a seven level cascaded multilevel inverter using phase-shifted carrier PWM (PSCPWM). This method is base on modifying the switching state without any external circuit. © 2013 IEEE. |
|---|