Search Results - parallel sequence optimization algorithm

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  1. 1

    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using asic design flow: article / Nurzaima Mahmod by Mahmod, Nurzaima

    “…The scope of this paper is to optimize the DNA sequences alignment on the matrix rilling module by implementing a parallel method of the Smith-Waterman algorithm. …”
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    Article
  2. 2

    Design and analysis of high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow / Nurzaima Mahmod by Mahmod, Nurzaima

    Published 2010
    “…The scope of this paper is to optimize the DNA sequences alignment on the matrix filling module by implementing a parallel method of the SmithWaterman algorithm. …”
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    Thesis
  3. 3

    Application of intelligence based genetic algorithm for job sequencing problem on parallel mixed-model assembly line by Noroziroshan, Alireza, Mohd Ariffin, Mohd Khairol Anuar, Ismail, Napsiah

    Published 2010
    “…Then, it started to find the best sequence of jobs for each line based on the generated population by heuristic algorithm. …”
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    Article
  4. 4

    Design and analysis of high performance and low power matrix filling for DNA sequence alignment accelerator using ASIC design flow: article by Abd Razak, Nurul Farhana

    Published 2009
    “…The objective of this paper is to improve the performance of the DNA sequence alignment and to optimize power reduction of the existing technique by using Smitt Waterman (SW) algorithm. …”
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    Article
  5. 5

    Design and development of high performance swa cell design for local DNA sequence alignment by Syed Abdul Rahman, Syed Abdul Mutalib Al Junid

    Published 2017
    “…This study proposed three new DNA sequence alignment accelerator system cell design and architecture based on the Smith-Waterman Algorithm (SWA) named as the new Optimized SWA Linear Gap Penalty (OSL), Optimized SWA Affine Gap Penalty (OSA), and Optimized Recursive Variable Expansion SWA Linear Gap Penalty (ORSL). …”
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    Thesis
  6. 6

    Probabilistic ensemble fuzzy ARTMAP optimization using hierarchical parallel genetic algorithms by Loo, C.K., Liew, W.S., Seera, M., Lim, Einly

    Published 2015
    “…A genetic algorithm search heuristic was chosen to solve this multi-objective optimization problem. …”
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    Article
  7. 7

    Design and analysis of high performance and low power matrix filling for DNA sequence allignment accelerator using ASIC design flow / Nurul Farhana Abd Razak by Abd Razak, Nurul Farhana

    Published 2010
    “…The objective of this paper is to improve the performance of the DNA sequence alignment and to optimize power reduction of the existing technique by using Smith Waterman (SW) algorithm. …”
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    Student Project
  8. 8

    Topology-aware hypergraph based approach to optimize scheduling of parallel applications onto distributed parallel architectures by Koohi, Sina Zangbari

    Published 2020
    “…Any optimization algorithm is suitable for only a specific domain of optimization problems. …”
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    Thesis
  9. 9

    Design and development of high performance swa cell design for local DNA sequence alignment / Syed Abdul Mutalib Al Junid Syed Abdul Rahman by Syed Abdul Rahman, Syed Abdul Mutalib Al Junid

    Published 2017
    “…This study proposed three new DNA sequence alignment accelerator system cell design and architecture based on the Smith-Waterman Algorithm (SWA) named as the new Optimized SWA Linear Gap Penalty (OSL), Optimized SWA Affine Gap Penalty (OSA), and Optimized Recursive Variable Expansion SWA Linear Gap Penalty (ORSL).…”
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    Book Section
  10. 10
  11. 11

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…Using, VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language) as design tool has the advantage in optimizing the pDSP hardware requirement with ease where varying the size of units such as register files (RF), program sequencer (PS), data address generator (DAG), arithmetic logic unit (ALU), multiply-accumulator (MAC) and shifter can be done by changing the data width or bit values. …”
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    Thesis