Search Results - parallel reduction designing algorithm*

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  1. 1
    Harmonic reduction in three-phase parallel connected inverter

    Harmonic reduction in three-phase parallel connected inverter by Younis, M.A.A., Rahim, N.A., Mekhilef, Saad

    Published 2009
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  2. 2
    Improved black-winged kite algorithm and finite element analysis for robot parallel gripper design

    Improved black-winged kite algorithm and finite element analysis for robot parallel gripper design by Haohao, Ma, As’arry, Azizan, Yanwei, Feng, Lulu, Cheng, Delgoshaei, Aidin, Ismail, Mohd Idris Shah, Ramli, Hafiz Rashidi

    Published 2024
    “…A response surface optimization model is constructed to determine the best design solution. The optimized design achieves a 33.12% reduction in maximum equivalent stress, a 1.47% decrease in total mass, and a 0.16% reduction in maximum total deformation. …”
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  3. 3
    Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems

    Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems by Shakeel Ahmed, Kamboh

    Published 2014
    “…A data parallel algorithm (DPA-EHD) is designed and implemented for the EHD equations. …”
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  4. 4
    Efficient Sequential and Parallel Routing Algorithms in Optical Multistage Interconnection Network

    Efficient Sequential and Parallel Routing Algorithms in Optical Multistage Interconnection Network by Abduh Kaid, Monir Abdullah

    Published 2005
    “…This routing problem is an NPhard problem. Many algorithms are designed by many researchers to perform this routing such as window method, sequential algorithm, degree-descending algorithm, simulated annealing algorithm, genetic algorithm and ant colony algorithm.This thesis explores two approaches, sequential and parallel approaches. …”
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  5. 5
    Design and analysis of high performance and low power matrix filling for DNA sequence allignment accelerator using ASIC design flow / Nurul Farhana Abd Razak

    Design and analysis of high performance and low power matrix filling for DNA sequence allignment accelerator using ASIC design flow / Nurul Farhana Abd Razak by Abd Razak, Nurul Farhana

    Published 2010
    “…The scope of study is by using the matrix filling method which is in parallel implementation of the SmithWaterman algorithm. …”
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  6. 6
    A proposed design for noise reduction algorithm in seismograph on high performance computing using F-K filter

    A proposed design for noise reduction algorithm in seismograph on high performance computing using F-K filter by I.A., Aziz, T., Sandran, N.S., Haron, M., Mehat

    Published 2008
    “…This paper proposes a design of noise reduction algorithm for seismic data on a High Performance Computing (HPC) environment. …”
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  7. 7
    Design and analysis of high performance and low power matrix filling for DNA sequence alignment accelerator using ASIC design flow: article

    Design and analysis of high performance and low power matrix filling for DNA sequence alignment accelerator using ASIC design flow: article by Abd Razak, Nurul Farhana

    Published 2009
    “…The scope of study is by using the matrix filling method which is in parallel implementation of the Smith-Waterman algorithm.…”
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  8. 8
    Effect of model simplification through manual reduction in number of surfaces on room acoustics simulation

    Effect of model simplification through manual reduction in number of surfaces on room acoustics simulation by Abd Jalil, Nurul Amira, Che Din, Nazli, Keumala, Nila, Abdul-Razak, Asrul Sani

    Published 2019
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  9. 9
    Extended Kalman Filter (EKF)-based modular-stack Vanadium Redox Flow Battery (V-RFB) prediction model development for reducing electrode contact resistance and parallelization current

    Extended Kalman Filter (EKF)-based modular-stack Vanadium Redox Flow Battery (V-RFB) prediction model development for reducing electrode contact resistance and parallelization curr... by Mohamed, Mohd Rusllim

    Published 2019
    “…On the other hands, three different cell geometries of V-RFB cell, namely square-, rhombus- and circular cell designs are evaluated at three different cases i.e. no flow (plain) channel, parallel channel and serpentine channel. …”
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    Research Report
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  10. 10
    Design and development of high performance swa cell design for local DNA sequence alignment

    Design and development of high performance swa cell design for local DNA sequence alignment by Syed Abdul Rahman, Syed Abdul Mutalib Al Junid

    Published 2017
    “…On top of that, minimal stages of computation cycle were proposed and introduced in OSL cell design, with a reduction of 25% compared to the previous SWA linear gap penalty design. …”
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  11. 11
    Deterministic Automatic Test Pattern Generation for Built-In Self Test System

    Deterministic Automatic Test Pattern Generation for Built-In Self Test System by Mohammed Khalid, Muhammad Nazir

    Published 2006
    “…To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. …”
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  12. 12
    FPGA implementation of MCPFSK modulation for HF data communication

    FPGA implementation of MCPFSK modulation for HF data communication by Fitri Dewi, Jaswar, Ahmad Zuri, Sha’ameri

    Published 2009
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  13. 13
    FPGA implementation of CPFSK modulation techniques for HF data communication

    FPGA implementation of CPFSK modulation techniques for HF data communication by Jaswar, Fitri Dewi, Sha'ameri, Ahmad Zuri

    Published 2003
    “…Further reduction in components is achieved hy adopting a multiplierless and parallel algorithm at the receiver module. …”
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  14. 14
    A modified artificial neural network (ANN) algorithm to control shunt active power filter (SAPF) for current harmonics reduction

    A modified artificial neural network (ANN) algorithm to control shunt active power filter (SAPF) for current harmonics reduction by Sabo, Aliyu, Abdul Wahab, Noor Izzri, Mohd Radzi, Mohd Amran, Mailah, Nashiren Farzilah

    Published 2013
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  15. 15
    Accelerating FPGA-surf feature detection module by memory access reduction

    Accelerating FPGA-surf feature detection module by memory access reduction by Mohd. Yamani Idna, Idris, Nor Bakiah, Abd. Warif, Hamzah, Arof, Noorzaily, Mohamed Noor, Ainuddin Wahid, Abdul Wahab, Zaidi, Razak

    Published 2019
    “…We also found that the SURF algorithm memory access has redundant repeating pattern that can be reduced. …”
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  16. 16
    Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi

    Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi by Hosseiny Fatemi, Mohammad Reza

    Published 2012
    “…For the hardware architecture design, we choose bit-serial structure for implementing our algorithm to benefit from its advantages. …”
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  17. 17
    Magnetic resonance imaging sense reconstruction system using FPGA / Muhammad Faisal Siddiqui

    Magnetic resonance imaging sense reconstruction system using FPGA / Muhammad Faisal Siddiqui by Muhammad Faisal , Siddiqui

    Published 2016
    “…Complex multiplier, complex matrix multiplier and pseudo-inverse modules are designed according to the algorithmic needs to increase the efficiency of the system. …”
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  18. 18
    A modified approach to improve the performance of AES using feistel structure

    A modified approach to improve the performance of AES using feistel structure by Al-Ansi, Afeef Yahya Ahmed

    Published 2018
    “…In encryption algorithm design, apart from the security performance, processing performance and the cost of the implementation are very important trade-off parameters. …”
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  19. 19
    New methods of partial transmit sequence for reducing the high peak-to-average-power ratio with low complexity in the ofdm and f-ofdm systems

    New methods of partial transmit sequence for reducing the high peak-to-average-power ratio with low complexity in the ofdm and f-ofdm systems by Abduljabbar, Yasir Amer

    Published 2019
    “…Third, a new hybrid method that combines the Selective mapping and Cyclically Shifts Sequences (SLM-CSS-PTS) techniques in parallel has been proposed for improving the PAPR reduction performance and the computational complexity level. …”
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  20. 20
    Improvement Of Solar Farm Efficiency And Energy Production By Using Distributed MPPPT

    Improvement Of Solar Farm Efficiency And Energy Production By Using Distributed MPPPT by Janesh Kiran A/L Kalaichelvan

    Published 2023
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