Search Results - parallel reduction ((using algorithm) OR (using (algorithmic OR algorithms)))*

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  1. 1
    Parallelization of noise reduction algorithm for seismic data on a beowulf cluster

    Parallelization of noise reduction algorithm for seismic data on a beowulf cluster by Aziz, I. A., Sandran, T., Haron, N. S., Hasan, M. H, Mehat, M.

    Published 2010
    “…This paper presents the parallelization of a sequential noise reduction algorithm for seismic data processing into a parallel algorithm. …”
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  2. 2
    A GPGPU Approach to Accelerate Ant Swarm Optimization Rough Reducts (ASORR) Algorithm

    A GPGPU Approach to Accelerate Ant Swarm Optimization Rough Reducts (ASORR) Algorithm by Udayanti, Erika Devi, Choo, Yun Huoy, Draman @ Muda, Azah Kamilah, Nugroho, Fajar Agung

    Published 2012
    “…Ant Swarm Optimization Rough Reducts (ASORR) algorithm is used in rough reducts calculation for identifying significant attribute set optimally. …”
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  3. 3
    Efficient Sequential and Parallel Routing Algorithms in Optical Multistage Interconnection Network

    Efficient Sequential and Parallel Routing Algorithms in Optical Multistage Interconnection Network by Abduh Kaid, Monir Abdullah

    Published 2005
    “…The first approach is to develop an efficient sequential algorithm for the window method. Reduction of the execution time of the algorithm in sequential platform, led to a massive improvement of the algorithm speed. …”
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  4. 4
    Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems

    Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems by Shakeel Ahmed, Kamboh

    Published 2014
    “…To implement the parallel algorithms a distributed parallel computing laboratory using easily available low cost computers is setup. …”
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  5. 5
    Fast Finite Difference Time Domain Algorithms for Solving Antenna Application Problem

    Fast Finite Difference Time Domain Algorithms for Solving Antenna Application Problem by Hasan, Mohammad Khatim

    Published 2008
    “…Complexity reduction approach concept is used to develop these algorithms. …”
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  6. 6
    Parallelization of speech compression based algorithm based on human auditory system on multicore system

    Parallelization of speech compression based algorithm based on human auditory system on multicore system by Gunawan, Teddy Surya, Kartiwi, Mira, Khalifa, Othman Omran

    Published 2012
    “…Finally, the performance of the developed parallel algorithm was evaluated using Perceptual Evaluation of Speech Quality (PESQ) and parallel execution time. …”
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  7. 7
    Enhancing speed performance of the cryptographic algorithm based on the lucas sequence

    Enhancing speed performance of the cryptographic algorithm based on the lucas sequence by M. Abulkhirat, Esam

    Published 2003
    “…Reducing the calculation time of the algorithm, in sequential and parallel platforms, using the doubling-rule technique combined with a new scheme led to a strong improvement of the LUC algorithm speed. …”
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  8. 8
    Design and analysis of high performance and low power matrix filling for DNA sequence alignment accelerator using ASIC design flow: article

    Design and analysis of high performance and low power matrix filling for DNA sequence alignment accelerator using ASIC design flow: article by Abd Razak, Nurul Farhana

    Published 2009
    “…The scope of study is by using the matrix filling method which is in parallel implementation of the Smith-Waterman algorithm.…”
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  9. 9
    A proposed design for noise reduction algorithm in seismograph on high performance computing using F-K filter

    A proposed design for noise reduction algorithm in seismograph on high performance computing using F-K filter by I.A., Aziz, T., Sandran, N.S., Haron, M., Mehat

    Published 2008
    “…The algorithm of interest is the F-k filter which can be optimized by executing it using parallel processing architecture. …”
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  10. 10
    Design and analysis of high performance and low power matrix filling for DNA sequence allignment accelerator using ASIC design flow / Nurul Farhana Abd Razak

    Design and analysis of high performance and low power matrix filling for DNA sequence allignment accelerator using ASIC design flow / Nurul Farhana Abd Razak by Abd Razak, Nurul Farhana

    Published 2010
    “…The scope of study is by using the matrix filling method which is in parallel implementation of the SmithWaterman algorithm. …”
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  11. 11
    Bitwise-based Routing Algorithms in Optical Multistage Interconnection Network

    Bitwise-based Routing Algorithms in Optical Multistage Interconnection Network by Abed, Farzaneh

    Published 2007
    “…Under the constraint of avoiding crosstalk, the interests of these algorithms are to find a permutation that uses a minimum number of passes and minimum execution time. …”
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  12. 12
    Improved black-winged kite algorithm and finite element analysis for robot parallel gripper design

    Improved black-winged kite algorithm and finite element analysis for robot parallel gripper design by Haohao, Ma, As’arry, Azizan, Yanwei, Feng, Lulu, Cheng, Delgoshaei, Aidin, Ismail, Mohd Idris Shah, Ramli, Hafiz Rashidi

    Published 2024
    “…This paper presents a comprehensive study on the design optimization of a robotic gripper, focusing on both the gripper modeling and the optimization of its parallel mechanism structure. This study integrates the Black-winged Kite Algorithm (BKA), Finite Element Analysis (FEA), Backpropagation Neural Network (BPNN), and response surface optimization techniques. …”
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  13. 13
    Harmonic reduction in three-phase parallel connected inverter

    Harmonic reduction in three-phase parallel connected inverter by Younis, M.A.A., Rahim, N.A., Mekhilef, Saad

    Published 2009
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  14. 14
    Finite element model for crack propagation using master-workers method

    Finite element model for crack propagation using master-workers method by Ahmad Kamal Ariffin, Choy , Hau Yan, Mohd Jailani Mohd Nor

    Published 2004
    “…This paper describes an algorithm for parallel assembling of the stiffness matrix in simulation of crack propagation in distributed memory environment using masterworkers method. …”
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  15. 15
    Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi

    Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi by Hosseiny Fatemi, Mohammad Reza

    Published 2012
    “…For the hardware architecture design, we choose bit-serial structure for implementing our algorithm to benefit from its advantages. Moreover, we use SAD truncation, reusability, source sharing, and power saving techniques in our architecture, which lead to area saving and power consumption reduction. …”
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  16. 16
    Energy-aware scheduling optimization in hybrid flow shops using artificial bee colony algorithm

    Energy-aware scheduling optimization in hybrid flow shops using artificial bee colony algorithm by Mohd Abdul Hadi, Osman, Mohd Fadzil Faisae, Ab Rashid, Nik Mohd Zuki, Nik Mohamed, Muhammad Ammar, Nik Mu’tasim

    Published 2024
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  17. 17
    New methods of partial transmit sequence for reducing the high peak-to-average-power ratio with low complexity in the ofdm and f-ofdm systems

    New methods of partial transmit sequence for reducing the high peak-to-average-power ratio with low complexity in the ofdm and f-ofdm systems by Abduljabbar, Yasir Amer

    Published 2019
    “…The results that obtained using the proposed methods achieve a superior gain in the PAPR reduction performance compared with the conventional PTS technique. …”
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  18. 18
    Greedyzero-based scheduling algorithm to route in optical low stage interconnection networks

    Greedyzero-based scheduling algorithm to route in optical low stage interconnection networks by Moudi, Mehrnaz

    Published 2012
    “…This algorithm has been developed to achieve performance goals in terms of 50% reduction in the number of passes.…”
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  19. 19
    A modified artificial neural network (ANN) algorithm to control shunt active power filter (SAPF) for current harmonics reduction

    A modified artificial neural network (ANN) algorithm to control shunt active power filter (SAPF) for current harmonics reduction by Sabo, Aliyu, Abdul Wahab, Noor Izzri, Mohd Radzi, Mohd Amran, Mailah, Nashiren Farzilah

    Published 2013
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  20. 20
    FPGA implementation of CPFSK modulation techniques for HF data communication

    FPGA implementation of CPFSK modulation techniques for HF data communication by Jaswar, Fitri Dewi, Sha'ameri, Ahmad Zuri

    Published 2003
    “…The proposed modulation integrates holh the transmitter and receiver modules into a single FPGA. Further reduction in components is achieved hy adopting a multiplierless and parallel algorithm at the receiver module. …”
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