Search Results - parallel operational tree algorithm

Robust partitioning and indexing for iris biometric database based on local features by Khalaf, Emad Taha, Mohammed, Muamer N., Kohbalan, Moorthy

“…Further, the scalable K-means++ algorithm is used for partitioning and classification processes, and an efficient parallel technique that divides the features groups causing the formation of two b-trees based on index keys is applied for search and retrieval. …”
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Energy-aware task scheduling for streaming applications on NoC-based MPSoCs by Abd Ishak, Suhaimi Abd Ishak, Wu, Hui, Tariq, Umair Ullah

“…Our approach is supported by a set of novel techniques, which include constructing an initial schedule based on a list scheduling where the priority of each task is its approximate successor-tree-consistent deadline such that the workload across all the processors is balanced, a retiming heuristic to transform intraperiod dependencies into inter-period dependencies for enhancing parallelism, assigning an optimal discrete frequency for each task and each message using a Non-Linear Programming (NLP)-based algorithm and an Integer-Linear Programming (ILP)-based algorithm, and an incremental approach to reduce the memory usage of the retimed schedule in case of memory size violations. …”
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Twofold Integer Programming Model for Improving Rough Set Classification Accuracy in Data Mining. by Saeed, Walid

“…The accuracy for rules and classification resulted from the TIP method are compared with other methods such as Standard Integer Programming (SIP) and Decision Related Integer Programming (DRIP) from Rough Set, Genetic Algorithm (GA), Johnson reducer, HoltelR method, Multiple Regression (MR), Neural Network (NN), Induction of Decision Tree Algorithm (ID3) and Base Learning Algorithm (C4.5); all other classifiers that are mostly used in the classification tasks. …”
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Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi by Hosseiny Fatemi, Mohammad Reza

“…The second design uses a 2-D bit-serial adder tree connected to a reconfigurable reference buffer making it suitable for hardware parallelism. …”
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