Search Results - parallel implementation real algorithm*

Design and implementation of a real-time adaptive learning algorithm controller for a 3-DOF parallel manipulator / Mustafa Jabbar Hayawi by Hayawi, Mustafa Jabbar

“…An electronic board, transistor relay driver circuit, is designed for the purpose of establishing communication interface between the computer, adaptive learning algorithm and the actuator mechanism. Design and development an adaptive learning algorithm controller ALAC of position the actuators is presented in real time parallel manipulator based on artificial neural network ANN. …”
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Development of a real-time clutch transition strategy for a parallel hybrid electric vehicle by Vu, Trieu Minh

“…The system can be implemented in electronic control units and applied for real HEVs.…”
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Development of Lifting-based VLSI Architectures for Two-Dimensional Discrete Wavelet Transform by MOHAMED KOKO, IBRAHIM SAEED

“…In order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed and throughput parallelism is explored. …”
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Resource Minimization in a Real-time Depth-map Processing System on FPGA by Ngo, Huy Tan, Hamid, Nor Hisham, Sebastian , Patrick, Yap, Vooi Voon

“…Depth-map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. …”
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Enhanced and effective parallel optical flow method for vehicle detection and tracking by Bhaskar, P.K., Yong, S.-P., Jung, L.T.

“…With a view to do improvements, it is proposed to develop an unique algorithm for vehicle data recognition and tracking using Parallel Optical Flow method based on Lucas-Kanade algorithm. …”
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Parallel Kalman filter-based multi-human tracking in surveillance video by Yussiff, A.-L., Yong, S.-P., Baharudin, B.B.

“…The parallel implementation has increased the frame processing speed by 20-30 percent over the CPU implementation. …”
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Sequential and parallel multiple tabu search algorithm for multiobjective urban transit scheduling problems by Uvaraja, Vikneswary

“…Additionally, the MTS algorithm is also implemented in parallel computing to produce parallel MTS for generating comparable solutions in shorter computational times. …”
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MOSIX: Implementation, trend and benchmark in Malaysia by Hakim M., Jais J., Salwa S.

Minimum rule-based parallel structure fuzzy controller by Karimadini, Mohammad, Marhaban, Mohammad Hamiruce, Mohd Noor, Samsul Bahari, Aris, Ishak, Davari, Atefeh

“…There is a trade off between approximation and memory space (algorithm cycle time). This paper proposes a simple parallel structure of fuzzy controllers where simulation is performed on a real temperature model. …”
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Efficient hardware design for palm-dorsa vein image enhancement by Jusoh@Yusoff, Suhaimi Bahisham

“…Hardware implementation can provide a solution to achieve real time performance. …”
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A parallel ensemble learning model for fault detection and diagnosis of industrial machinery by Shing, Chiang Ta, Mohammed Al-Andoli, Mohammed Nasser, Kok, Swee Sim, Seera, Manjeevan, Chee, Peng Lim

“…These findings indicate that the proposed model is effective and efficient for FDD of industrial machinery, making it a promising solution for implementation in real-world environments.…”
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OPTIMIZED ARCHITECTURE DESIGN AND IMPLEMENTATION OF OBJECT TRACKING ALGORITHM ON FPGA by ABDELFATAH EL-KHATIB, LINA NOAMAN

“…This research work aims at optimizing the device utilization under real time constraints. The Adaptive Hybrid Difference algorithm (AHD), which is used to detect the moving objects, was chosen to be implemented on FPGA due to its computation ability and efficiency with regard to hardware implementation. …”
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Skin region detector for real time face detection system by Mohd Mustafah, Yasir, Azman, Amelia Wong

“…In the implementation, the region of interest is detected using two algorithms, running in parallel. …”
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Parallel metaheuristic algorithm for route planning using CUDA by Looi, Daniel Jun Jie

“…Besides, this research strives to provide a foundation for future research on parallel metaheuristic algorithms, and to further encourage their implementations in real-world instances of route planning. …”
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Face recognition using artificial neural networks in parallel architecture by Omarov B., Suliman A., Kushibar K.

“…There, we consider a parallel training approach for backpropagation algorithm for face recognition. …”

A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder by Mabrouk, Ahmed Hassan, Hassim, Norhidayah

“…Module speeds are reported in terms of the number of clock cycles taken by each of their sub-modules to show suitability for real-time applications. Synthesis results are reported using various degrees of parallelism to explore the trade-off between gate count and time delay. …”
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MINIMIZATION OF RESOURCE UTILIZATION FOR A REAL-TIME DEPTH-MAP COMPUTATIONAL MODULE ON FPGA by NGO , NGO HUY TAN

“…In this thesis, five different depth-map processor architectures for the sum-of-absolute-difference (SAD) depth-map algorithm on FPGA at real-time were designed and implemented. …”
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Distributed parallel deep learning with a hybrid backpropagation-particle swarm optimization for community detection in large complex networks by Shing, Chiang Ta, Mohammed Al-Andoli, Mohammed Nasser, Wooi, Ping Cheah

“…In this paper, a parallel deep learning-based community detection method in large complex networks (CNs) is proposed. …”
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FPGA-enabled binarised convolutional neural networks toward real-time embedded object recognition system by Shuto, Daisuke, Abbas, Z., Sulaiman, N., Tamukoh, H.

“…To overcome these difficulties, we propose an embedded object recognition system implemented with a binarised CNN and an FPGA. FPGAs consist of a matrix of reconfigurable logic gates allowing parallel computing which befits most image processing algorithms such as the CNN. …”
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Speed Efficient Hardware Implementation Of Advanced Encryption Standard (Aes) by Low, Chiau Thian

“…This thesis presents a high throughput design of the 128-bit AES algorithm using loop unrolling, pipelined architecture and LUT approach which is able to work in parallel to allow accurate synchronization in order to fulfill the real time application needs. …”
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