Search Results - parallel digitalization approach algorithm

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  1. 1
    Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture

    Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture by Eessa, Mohammed F.

    Published 2015
    “…By assuming that parallel architectures are forming the vast majority of computing nodes in digital devises, proposing inherently-parallel algorithms are no more an overstatement. …”
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  2. 2
    Deterministic Automatic Test Pattern Generation for Built-In Self Test System

    Deterministic Automatic Test Pattern Generation for Built-In Self Test System by Mohammed Khalid, Muhammad Nazir

    Published 2006
    “…To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. …”
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  3. 3
    Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method

    Digital Quran With Storage Optimization Through Duplication Handling And Compressed Sparse Matrix Method by Ashraf Saleh Mohammad Alomoush

    Published 2024
    thesis::doctoral thesis
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  4. 4
    Quantification and segmentation of breast cancer diagnosis: efficient hardware accelerator approach

    Quantification and segmentation of breast cancer diagnosis: efficient hardware accelerator approach by Othman, Khairulnizam

    Published 2022
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  5. 5
    Speech compression using compressive sensing on a multicore system

    Speech compression using compressive sensing on a multicore system by Gunawan, Teddy Surya, Khalifa, Othman Omran, Shafie, Amir Akramin, Ambikairajah, Eliathamby

    Published 2011
    “…Finally, to speed up the process, the proposed algorithm will be implemented in a multicore system, i.e. six cores, using Single Program Multiple Data (SPMD) parallel paradigm.…”
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  6. 6
    A QoS guaranteed link adaptation packet transmission in IEEE 802.11ac WLAN / Aliya Syahira Mohd Anuar

    A QoS guaranteed link adaptation packet transmission in IEEE 802.11ac WLAN / Aliya Syahira Mohd Anuar by Mohd Anuar, Aliya Syahira

    Published 2022
    “…The rising demand for digital communication technologies has contributed to the increase in traffic intensity which in turn, has led to a congested network. …”
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  7. 7
    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

    Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture by Lee, Lini @ Lini Lee

    Published 2001
    “…However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. …”
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  8. 8
    An Improve k-NN Classifier using Similarity Distance Plot-Data Reduction and Dask for Big Datasets

    An Improve k-NN Classifier using Similarity Distance Plot-Data Reduction and Dask for Big Datasets by Abdul Muqtasid, Rushdi

    Published 2025
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  9. 9
    High-Speed Implementations Of Fractal Image Compression For Low And High Resolution Images

    High-Speed Implementations Of Fractal Image Compression For Low And High Resolution Images by Saad, Abdul Malik Haider Yusef

    Published 2018
    “…Therefore, in this research new hardware implementations of FIC are proposed for accelerating the encoding process by means of parallelism and pipelining. Various approaches have been investigated for achieving high speed performance. …”
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  10. 10
    Authenticating sensitive diacritical texts using residual, data representation and pattern matching methods / Saqib Iqbal Hakak

    Authenticating sensitive diacritical texts using residual, data representation and pattern matching methods / Saqib Iqbal Hakak by Saqib Iqbal , Hakak

    Published 2018
    “…The searching of halves is achieved through two different algorithms based on the split approach and the parallel approach respectively. …”
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  11. 11
    An Efficient Energy Aware Adaptive System-On-Chip Architecture For Real-Time Video Analytics

    An Efficient Energy Aware Adaptive System-On-Chip Architecture For Real-Time Video Analytics by Ahmed, Hisham Ahmed Ali

    Published 2016
    “…A careful analysis of the algorithm and efficient utilization of Zynq resources results in highly parallelized and pipelined architecture outperforms the state-of-the-art. …”
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