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  1. 1
    Efficient Sequential and Parallel Routing Algorithms in Optical Multistage Interconnection Network

    Efficient Sequential and Parallel Routing Algorithms in Optical Multistage Interconnection Network by Abduh Kaid, Monir Abdullah

    Published 2005
    “…This routing problem is an NPhard problem. Many algorithms are designed by many researchers to perform this routing such as window method, sequential algorithm, degree-descending algorithm, simulated annealing algorithm, genetic algorithm and ant colony algorithm.This thesis explores two approaches, sequential and parallel approaches. …”
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  2. 2
    Line clipping based on parallelism approach and midpoint intersection

    Line clipping based on parallelism approach and midpoint intersection by Hattab, Adel Salem Abdullah, Yusof, Yuhanis

    Published 2014
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  3. 3
    Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems

    Parallel algorithms for numerical simulations of EHD ion-drag micropump on distributed parallel computing systems by Shakeel Ahmed, Kamboh

    Published 2014
    “…To implement the parallel algorithms a distributed parallel computing laboratory using easily available low cost computers is setup. …”
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  4. 4
    Efficient hardware design for palm-dorsa vein image enhancement

    Efficient hardware design for palm-dorsa vein image enhancement by Jusoh@Yusoff, Suhaimi Bahisham

    Published 2018
    “…For hardware design of thinning, parallel pipelined with Concurrent Condition Check Unit hardware architecture has been developed to enable the parallelism of the thinning algorithm. …”
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  5. 5
    Resource Minimization in a Real-time Depth-map Processing System on FPGA

    Resource Minimization in a Real-time Depth-map Processing System on FPGA by Ngo, Huy Tan, Hamid, Nor Hisham, Sebastian , Patrick, Yap, Vooi Voon

    Published 2011
    “…Depth-map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. …”
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    MINIMIZATION OF RESOURCE UTILIZATION FOR A REAL-TIME DEPTH-MAP COMPUTATIONAL MODULE ON FPGA

    MINIMIZATION OF RESOURCE UTILIZATION FOR A REAL-TIME DEPTH-MAP COMPUTATIONAL MODULE ON FPGA by NGO , NGO HUY TAN

    Published 2011
    “…The algorithm is computationally intensive and therefore more effective to be implemented on hardware such as the Field Programmable Gate Array (FPGA). …”
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  7. 7
    Development of appoinment scheduling agent using distributed constraint satisfaction (DisCS)

    Development of appoinment scheduling agent using distributed constraint satisfaction (DisCS) by Mohd. Azmi, Nurulhuda Firdaus, Eri, Zeti Darleena, Ibrahim, Nuzulha Khilwani, Ahmad Rusli, Rozana Diana

    Published 2008
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  8. 8
    Online teleoperation of writing manipulator through graphics processing unit based accelerated stereo vision

    Online teleoperation of writing manipulator through graphics processing unit based accelerated stereo vision by Abu Raid, Fadi Imad Osman

    Published 2021
    “…These algorithms are then parallelized using Compute Unified Device Architecture CUDA C language to run on Graphics Processing Unit GPU for hardware acceleration. …”
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  9. 9
    A hybrid rate control mechanism for forwarding and congestion control in named data network

    A hybrid rate control mechanism for forwarding and congestion control in named data network by Alsamman, Mohammed Gamal

    Published 2020
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  10. 10
    Adaptive persistence layer for synchronous replication (PLSR) in heterogeneous system

    Adaptive persistence layer for synchronous replication (PLSR) in heterogeneous system by Beg, Abul Hashem

    Published 2011
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