Search Results - (programme OR program) (gate OR (date OR data)) array

Multipoint Detection Technique With The Best Clock Signal Closed-Loop Feedback To Prolong FPGA Performance by Soin, Norhayati, Zakaria, Zahriladha, Salim, Sani Irwan, Jaafar, Anuar, Wan Muhamad Hatta, Sharifah Fatmadiana

“…The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. …”
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FPGA configuration on Xilinx ML506 development board through the USB port in C/HDL by Kushal, Sreedhar

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Field programmable gate array based three-phase PWM inverter by Mekhilef, Saad, Rahim, N.A.

“…Its main function is to control the switching sequence of the power devices according to per-loaded instruction. Using Field Programmable Gate Array (FPGA) technology all the functions can be implemented in a single chip. …”
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Design Of Direct Sequence Code Division Multiple Access (Ds-Cdma) Wireless Transmitter Using Field Programmable Gate Array (Fpga) by Osman, Khalid Eltahir Mohamed

“…This thesis describes the DS-CDMA wireless transmitter design using FPGA (Field Programmable Gate Array), which has been adopted in many wireless access technologies. …”
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A Simple Approach of Space-vector Pulse Width Modulation Realization Based on Field Programmable Gate Array by Sutikno, Tole, Jidin, Auzani, Wong, Jenn Hwa, Nik Idris, Nik Rumzi

“…Employing a field programmable gate array to realize space-vector pulse width modulation is a solution to boost system performance. …”
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Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

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Advanced encryption standard-XTS implementation in field programmable gate array hardware by Ahmed, Shakil, Samsudin, Khairulmizam, Ramli, Abdul Rahman, Rokhani, Fakhrul Zaman

“…This standard uses Advanced Encryption Standard-XEX weakable block cipher with ciphertext stealing as a building block for the protection of data. Few field programmable gate array-based implementations of this mode that achieve sustainable throughput for block storage devices exist. …”
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Booth’s Algorithm Design Using Field Programmable Gate Array by Ab Hadi, Nik Azran, A Aziz, Khairul Azha, Hashim, Nik Mohd Zarifie, Omar, Muhammad Shukri, Jaafar, Anuar

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Division Algorithm Design Using Field Programmable Gate Array by Jaafar, Anuar, Mad Lazim, Muzafirah, Hashim, Nik Mohd Zarifie, Salleh, Azahari, Ja'afar, Abd Shukur

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Design and implementation of a direct torque control of induction machine utilizing a digital signal processor and the field programmable gate arrays by Toh, C. L., Idris, Nik Rumzi, Yatim, A. H. M., Patkar, Fadzli

“…A special class of ASIC known as Field Programmable presents a high performance DTC induction motor drive with Gate Arrays (FPGA's) offers a realistic alternative. …”
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FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection by Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Ping L.C.

“…Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. …”

FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

Subjects: “…Field programmable gate arrays…”
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Floating point multiplication unit using FPGA by Woon Woei Zit

Subjects: “…Field programmable gate arrays…”
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Matlab modeled for real time processing of partial discharge detection using fpga technology with giga hertz data acquisition by Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Devkumar S., Hock G.C., Badjian M.H.

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THREE BIT SUBTRACTION CIRCUIT VIA FIELD PROGRAMMABLE by Jaafar, Anuar, ARASID, NOORAISYAH, Hashim, Nik Mohd Zarifie, Abdul Latiff, anas, Abdul Rahim, Hazli Rafis

“…This project is about to design the software and hardware simulator for a Three Bit subtraction Circuit via Field Programmable Gate Array (FPGA). The three bit subtraction circuits are involved in performing the subtraction for each bit by performs operation the arithmetic and logic unit, called the Arithmetic Logic Unit (ALU). …”
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Two-Step Implementation of Sigmoid Function for Artificial Neural Network in Field Programmable Gate Array by Syahrulanuar, Ngah, Rohani, Abu Bakar, Abdullah, Embong

“…In this paper, a combination of second order nonlinear function (SONF) and differential look-up table (differential LUT) is introduced as a sigmoid function for implementing the artificial neural network (ANN) in field programmable gate array (FPGA). Implementing ANN on FPGA will overcome the slow response for real-time application and portable issues that arise in the software-based ANN. …”
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Simple-As-Possible Computer System Development on Field Programmable Gate Array by Lee, Siang Yeek

“…This report presents the project work and results of the Simple-As-Possible (SAP) computer system development on Field Programmable Gate Array (FPGA) project. This project undertaken as fulfilment of the two semesters EEB5034 & EEB5044 Final Year Project course is aimed to develop the first generation of SAP computer (SAP-1) introduced by Albert Paul Malvino on FPGAs for educational purpose. …”
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Indoor positioning using artificial neural network with field programmable gate array implementation by Syahrulanuar, Ngah, Rohani, Abu Bakar, Suryanti, Awang

“…To speed up the calculation time, ANN then is run into field programmable gate array (FPGA). Since the original sigmoid function in ANN is not feasible to be applied into FPGA, two-steps sigmoid function calculation proposed by previous researcher then is used as a replacement. …”
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Two-Steps Implementation of Sigmoid Function for Artificial Neural Network in Field Programmable Gate Array by Syahrulanuar, Ngah, Rohani, Abu Bakar, Abdullah, Embong, Saifudin, Razali

“…The complex equation of sigmoid function is one of the most difficult problems encountered for implementing the artificial neural network (ANN) into a field programmable gate array (FPGA). To overcome this problem, the combination of second order nonlinear function (SONF) and the differential lookup table (dLUT) has been proposed in this paper. …”
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Delay Performance Due To Thermal Variation On Field-Programmable Gate Array Via The Adoption Of A Stable Ring Oscillator by Soin, Norhayati, Salim, Sani Irwan, Jaafar, Anuar, Wan Muhamad Hatta, Sharifah

“…Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. …”
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