Search Results - (( verification implementation path algorithm ) OR ( java segmentation using algorithm ))

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  1. 1

    Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area by Lim , Yen Ruen

    Published 2017
    “…Among all of the cryptography measures, Secure Hash Algorithm 3 (SHA-3) is the newest and secure cryptographic hash algorithm in the current electronic industry. …”
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    Thesis
  2. 2

    Image clustering comparison of two color segmentation techniques by Subramaniam, Kavitha Pichaiyan

    Published 2010
    “…Finally, the algorithm found, which would solve the image segmentation problem.…”
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    Thesis
  3. 3

    Design and Implementation of MDS Hash Function Algorithm Using Verilog HDL by Shamsiah, Suhaili, Cleopatra Chundang, Niam, Zainah, Md. Zain, Norhuzaimin, Julai

    Published 2020
    “…A few distinct applications of hash algorithms are digital signatures, digital time stamping and the message integrity verification. …”
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    Article
  4. 4

    Development of web-based GIS for traffic management system with obstacle avoidance technique using open source software by Nik Yusoff, Nik Mohd Ramli

    Published 2014
    “…In order to calculate the shortest path between two nodes, Dijkstra algorithm was utilized. …”
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    Thesis
  5. 5

    Design and implementation of MD5 hash function algorithm using verilog HDL by Shamsiah, Suhaili, Niam, Cleopatra Chundang, Zainah, Md Zain, Norhuzaimin, Julai

    Published 2022
    “…A few distinct applications of hash algorithms are digital signatures, digital time stamping and the message integrity verification. …”
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    Conference or Workshop Item
  6. 6

    Automatic Number Plate Recognition on android platform: With some Java code excerpts by ., Abdul Mutholib, Gunawan, Teddy Surya, Kartiwi, Mira

    Published 2016
    “…On the other hand, the traditional algorithm using template matching only obtained 83.65% recognition rate with 0.97 second processing time. …”
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    Book
  7. 7
  8. 8

    A novel large-bit-size architecture and microarchitecture for the implementation of Superscalar Pipeline VLIW microprocessors by Lee, Weng Fook

    Published 2008
    “…An adder algorithm using repetitive constructs in a parallel algorithm that allows for efficient and optimal synthesis for large data bus size is proposed as a suitable implementation for the adder within the ALU. …”
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    Thesis
  9. 9

    Low power pipelined FFT processor architecture on FPGA by Mohd Hassan, Siti Lailatul, Sulaiman, Nasri, Abdul Halim, Ili Shairah

    Published 2018
    “…The simulation part is done via Modelsim and verification through Matlab. While the implementation is done via Quartus on the Altera Cyclone IV FPGA board. …”
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    Conference or Workshop Item