Search Results - (( using function method algorithm ) OR ( gate operation method algorithm ))

Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm by Chong, Kok Hen

“…The results show that the proposed method is able to produce the optimized circuit with lesser number of gates compared to the conventional methods. …”
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Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam by Meera , Subramaniam

“…This work presents a modification to the previous Signed Digit (SD) Generation algorithm and a comparison with the previous method. …”
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Developed method of FPGA-based fuzzy logic controller design with the aid of conventional PID algorithm by Obaid, Zeyad Assi, Sulaiman, Nasri, Hamidon, Mohd Nizar

“…This paper proposes developed method to design a digital fuzzy logic controller with the aid of conventional Proportional – integral – derivative (PID) controller using field programmable gate array (FPGA). …”
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An Improved FPGA Implementation of Direct Torque Control for Induction Machines by Jidin, Auzani

“…The Hardware-in-the-Loop (HiL) method is used to verify the functionality of the FPGA estimator. …”
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Multi-directional matrix converter for low power application using field-programmable gate array by Toosi, Saman

“…This study also derived necessary equation for proposed modulation method as well as detail of analysis and modulation algorithm. …”
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Improved genetic algorithm for direct current motor high speed controller implemented on field programmable gate array by Alkhafaji, Falih Salih

“…The third methodology is to integrate the proposed controller on FPGA, using a new method to run the design based simulink model. …”
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An Improved FPGA Implementation of Direct Torque Control for Induction Machines by Sutikno, Tole, Nik Idris, Nik Rumzi, Jidin , Auzani, Marcian, N. Cirstea

“…The Hardware-in-the-Loop method is used to verify the functionality of the FPGA estimator. …”
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IRFOC induction motor with rotor time constant estimation modelling and simulation by Radwan, E., Mariun, N., Aris, I., Bash, S. M., Yatim, Abdul Halim Mohamad

“…Purpose– To provide a new and simple inverse rotor time constant identification method which can be used to update an indirect rotor field oriented controlled (IRFOC) induction motor algorithm.Design/methodology/approach– Two different equations are used to estimate the rotor flux in the stator reference frame. …”
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Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

“…The Fast Fourier Transform (FFT) is an efficient method to achieve the Discrete Fourier Transform (DFT) with less number of operations. …”
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Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264 by Fatemi, M.R.H., Ates, H.F., Salleh, R.

“…In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. …”
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Optimization of reservoir operation at Klang Gate Dam utilizing a whale optimization algorithm and a L�vy flight and distribution enhancement technique by Lai V., Huang Y.F., Koo C.H., Ahmed A.N., El-Shafie A.

“…Taking it further, the KGD was studied using the nature-inspired meta-heuristic algorithms (MHAs). The Whale Optimisation Algorithm (WOA) solves complex technical issues. …”

Enhancing performance of XTS cryptography mode of operation using parallel design by Ahmed Alomari, Mohammad

“…To fully utilize the performance potential of XTS mode of operation, a parallel design for the algorithm is proposed. …”
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A 2x2 bit multiplier using hybrid 13 t full adder with vedic mathematics method by Lee, Shing Jie, Ruslan, Siti Hawa

“…The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. …”
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A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method by Lee, Shing Jie, Ruslan, Siti Hawa

“…The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. …”
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Gravitational Search Algorithm based Long Short-term Memory Deep Neural Network for Battery Capacity and Remaining Useful Life Prediction with Uncertainty by Reza M.S., Hannan M.A., Mansor M., Ker P.J., Tiong S.K., Hossain M.J.

“…The method proposed in this work is evaluated based on the aging data from the NASA battery dataset, and its effectiveness is compared with that of BiLSTM, baseline gated recurrent unit (GRU), and baseline LSTM using various error metrics. …”

Optimal water supply reservoir operation by leveraging the meta-heuristic Harris Hawks algorithms and opposite based learning technique by Lai V., Huang Y.F., Koo C.H., Ahmed A.N., Sherif M., El-Shafie A.

“…In this study, an attempt via metaheuristic algorithms, namely the Harris Hawks Optimisation (HHO) Algorithm and the Opposite Based Learning of HHO (OBL-HHO) are made to minimise the water deficit as well as mitigate floods at downstream of the Klang Gate Dam (KGD). …”

Design of field programmable gate array-based proportional-integral-derivative fuzzy logic controller with tunable ganin by Obaid, Zeyad Assi

“…Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as Field Programmable Gate Array (FPGA) can be used to integrate large amounts of logic in a single IC. …”
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FPGA Implementation of Emergency Door Car Entry System by Zaini Sulaiman

“…VHDL can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. Verilog is of the same goal, but it is written using a different format. …”
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Finding the root of nonlinear function using five bracketing method / Nur Afiqah Mohamed Azhar by Mohamed Azhar, Nur Afiqah

“…Therefore, numerical method in the form of bracketing method is often used to find only the approximate root of the function. …”
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State-of-charge estimation for lithium-ion batteries with optimized self-supervised transformer deep learning model by Dickson Neoh Tze How, Dr.

“…In the second stage, the model is fine-tuned or re-trained using labeled data with supervised learning. To evaluate its effectiveness, the Transformer model is benchmarked against various commonly used DL architectures such as Long Short-Term Memory(LSTM), Gated Recurrent Unit(GRU), Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). …”