Search Results - (( programme data array ) OR ( ((programme khaled) OR (programmes based)) array ))

Field programmable gate array based three-phase PWM inverter by Mekhilef, Saad, Rahim, N.A.

“…Its main function is to control the switching sequence of the power devices according to per-loaded instruction. Using Field Programmable Gate Array (FPGA) technology all the functions can be implemented in a single chip. …”
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Advanced encryption standard-XTS implementation in field programmable gate array hardware by Ahmed, Shakil, Samsudin, Khairulmizam, Ramli, Abdul Rahman, Rokhani, Fakhrul Zaman

“…This standard uses Advanced Encryption Standard-XEX weakable block cipher with ciphertext stealing as a building block for the protection of data. Few field programmable gate array-based implementations of this mode that achieve sustainable throughput for block storage devices exist. …”
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Delay Performance Due To Thermal Variation On Field-Programmable Gate Array Via The Adoption Of A Stable Ring Oscillator by Soin, Norhayati, Salim, Sani Irwan, Jaafar, Anuar, Wan Muhamad Hatta, Sharifah

“…Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. …”
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Design and implementation of real data fast fourier transform processor on field programmable gates array by Ahmed, Mohammed Kassim

“…In this work, the memorybased FFT processor, based on radix-4 FFT algorithm is implemented on Cyclone II Field Programmable Gates Array (FPGA). …”
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Improved field programmable gatearraybased accelerator of deep neural networkusing opencl by Yap, June Wai

“…Being compute-intensive and memory expensive, it is hard to deploy Deep Neural Network (DNN) based models into the embedded devices. Despite recent studies that have shown the efforts to explore the Field Programmable Gate Array (FPGA) as an alternative to deploy DNN-based models such as AlexNet and VGG, there is still a lot of challenges to implement DNN-based object detection model on Field Programmable Gate Array (FPGA). …”
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Optimization and analysis of FPGA-based systolic array for matrix multiplication by Shapri, Ahmad Husni Mohd, Rahman, Norazeani Abdul, Zakaria, Syed Muhammad Mamduh Syed, Chieh, Kiu Kwong, Saat, Shakir

“…Over the years, field-programmable gate array (FPGA)-based accelerators have attracted interest and attention due to their performance and energy efficiency factors. …”
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Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA by Shahadi H.I., Jidin R., Way W.H.

Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator by Jaafar, Anuar, Soin, Norhayati, Hatta, Sharifah Fatmadiana Wan Muhamad, Irwan Md, Salim Sani

“…Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. …”
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Design of DNA sequence alignment accelerated system using 2-dimensional array and custom instruction on FPGA / Nur Dalilah Ahmad Sabri by Ahmad Sabri, Nur Dalilah

“…Other than that, an implementation of a platform called Field Programmable Gate Array (FPGA) has been used in optimizing the 2D Array to perform accelerate sequence alignment activities. …”
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Digital beamforming implementation of switch-beam smart antenna system by using integrated digital signal processor and field-programmable gate array by Vakilian, Vida

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Stimulus signal generation for field programmable gate array- based gamma spectroscopy system by Abd Rahman, Nur Aira

“…Code simulation or test bench enables verification of new Field Programmable Gate Array (FPGA) design to be done during code development stage. …”
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Fast fourier transform processor implementation for high inputs on field programmable gates array by Ali Abbas, Zaid

“…Therefore, this research aims to investigate the power consumption, hardware resources usage and speed for radix-(2, 4 and 8) FFT processor, using the same device and environment to investigate the performance of each. Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). …”
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Improved genetic algorithm for direct current motor high speed controller implemented on field programmable gate array by Alkhafaji, Falih Salih

“…The main objective is to improve the speed performance of DC motor based PI controller in terms of dead (td), rise time(tr), settling times(ts) by estimating precise TF, improving GA performances, and enhancing architecture design to be integrated on Field Programmable Gate Array(FPGA). …”
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Compiler-based prefetching algorithm for recursive data structure by Anuar, Nurulhaini

“…Software prefetching has been shown to be effective in reducing memory stalls in array-based applications but not in pointer-based applications. …”
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Mobile application learning programme to learn fundamental of data structure using Gagne's learning style / Muhammad Syafiq Izzuddin Bahrin by Muhammad Syafiq Izzuddin Bahrin

“…Besides, most of the studies declared that a major drawback for beginner programmer is having weak skills on planning and outline This android-based mobile application is design for learners who want to learn about fundamental ofdata structure especially for Computer Science students. …”
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Fpga-Based Accelerator for The Generation of Pseudo-Amino Acid Composition by Ching, Chee Chow

“…Programmable hardware such as Field Programmable Gate Array (FPGA) enables parallel processing that speeds up computation of PseAAC. …”
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PRINCE IP-core on Field Programmable Gate Arrays (FPGA) by Abbas Y.A., Jidin R., Jamil N., Z'aba M.R., Rusli M.E.

“…This study presents a high execution-speed and low-resource hardware IP-Core of PRINCE light weight block cipher on a Field Programmable Gate Arrays (FPGA). The new FPGA IP-core is to speed-up the performance of PRINCE, superseding software implementation that is typically slow and inefficient. …”

Low area Programmable Memory Built-In Self-Test (PMBIST) for small embedded ram cores / Nur Qamarina Mohd Noor by Mohd Noor, Nur Qamarina

“…It is justified that the cluster technique provides full-speed test and low area overhead for the programmable memory BIST controller. The proposed clustered FSM-based and microcode-based P-MBIST achieves around 15% and 32% of area reduction respectively. …”
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FPGA implementation of MCPFSK modulation for HF data communication by Fitri Dewi, Jaswar, Ahmad Zuri, Sha’ameri

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Programming in C for foundation by Bakar, Noor Hasrina, Hassan, Noor Azimah, Idris, Mohd Norhaedir, Al-Shawabkeh, Mahmoud

“…Many advanced topics of “Arrays” and “Strings” are discussed. Search and sort as well as passing arrays between functions are demonstrated in chapter 5 the longest chapter in the book. …”
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